Proof-of-work acquisition device and method, electronic equipment and storage medium

Abstract

The invention provides a proof-of-work obtaining device and method, electronic equipment, a storage medium and a program, and belongs to the technical field of computers. According to the device, data sets used for executing the obtaining process of the workload proof are dispersed and stored on storage parts of different chips, so that during actual processing, the data sets dispersed on the storage parts of the different chips are summarized to an algorithm logic part of the same chip to execute the obtaining process of the workload proof; therefore, the storage space of the storage part in the chip can be used for storing part of the data set when the complete data set cannot be stored, the utilization rate of the storage space in the chip is improved, and the capability of obtaining the proof of work of the chip is improved.

Description

technical field [0001] The present application belongs to the field of computer technology, and in particular relates to a proof-of-work acquisition device, method, electronic equipment, storage medium and program. Background technique [0002] In the related technology, the memory-intensive algorithm needs to repeatedly extract a large amount of data from the memory randomly for operation during the operation process, and find a nonce (random value) to input into the algorithm, so that the obtained result is lower than a value based on a specific difficulty value. threshold. [0003] Therefore, the performance bottleneck of memory-intensive algorithms is memory bandwidth, which prevents multi-core parallel processing capabilities from being fully utilized, reduces the computing advantages of customized ASIC chips, and makes performance only related to memory size. However, due to manufacturing cost and process limitations, the memory capacity packaged in the chip is limite...

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Problems solved by technology

[0003] Therefore, the performance bottleneck of memory-intensive algorithms is memory bandwidth, which prevents multi-core parallel processing capabilities from being fully utilized, reduces the computing advantages of customized ASIC chips, and makes performance only related to memory size.

However, due to manufacturing cost and process limitations, the memory capacity packaged in the chip is limited and cannot be upgraded. As a result, when the data sets stored in some chips that perform specific functions continue to increase according to specific rules, and the data sets that need to be stored are larger than the memory capacity, The chip cannot continue to work, causing great waste

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