Circuit and method for flexibly setting delay time between instructions in CPU

A technology of delay time and configuration instructions, applied in the direction of machine execution devices, etc., can solve the problems of low delay accuracy, high power consumption, and inability to set arbitrary values, and achieve the effect of extremely small circuit overhead

Pending Publication Date: 2022-04-08
天津国芯科技有限公司
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  • Abstract
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  • Application Information

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Problems solved by technology

[0021] In view of this, the present invention aims to propose a circuit and method for flexibly setting the delay time between instructions in the CPU, so as to solve the pr

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  • Circuit and method for flexibly setting delay time between instructions in CPU
  • Circuit and method for flexibly setting delay time between instructions in CPU
  • Circuit and method for flexibly setting delay time between instructions in CPU

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Embodiment Construction

[0043] It should be noted that, in the case of no conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other.

[0044]In describing the present invention, it should be understood that the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", " The orientations or positional relationships indicated by "vertical", "horizontal", "top", "bottom", "inner" and "outer" are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and Simplified descriptions, rather than indicating or implying that the device or element referred to must have a particular orientation, be constructed and operate in a particular orientation, and thus should not be construed as limiting the invention. In addition, the terms "first", "second", etc. are used for descriptive purposes only, and should not be understood a...

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PUM

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Abstract

The invention provides a circuit and a method for flexibly setting delay time between instructions in a CPU (Central Processing Unit), which comprises the following specific steps of: adding a CPU configuration register configuration instruction at a program position between the instructions needing to be inserted with a time interval, and setting the delay time; when the CPU executes the CPU configuration register configuration instruction, configuration information is written into a configuration register corresponding to the CPU configuration register configuration instruction, and the configuration register sends a pause request to the existing external debugging control circuit to trigger the CPU to enter an idle state mechanism; when the CPU is in an idle state, the countdown timer enters a countdown working state; and monitoring the decline value of the countdown timer in each cycle, when the countdown timer is reduced to 0, sending an operation request to the existing external debugging control circuit, quitting the CPU from the idle state, and starting to continuously execute the subsequent program by the CPU. The invention discloses a circuit and a method which are used in an embedded CPU (Central Processing Unit) and are used for flexibly adding any specified delay interval between any two instructions as required.

Description

technical field [0001] The invention belongs to the field of CPU delay control, in particular to a circuit and a method for flexibly setting the delay time between instructions in a CPU. Background technique [0002] The CPU (Central Processing Unit) is the center of interpreting and executing software instructions in the chip. In debugging and practical applications, it is often necessary to insert a delay at a certain position in the program when executing the program. In practical applications, programmers often implement it by inserting several NOP instructions (empty instructions without actual operation). A typical program example looks like this: [0003] STORE(data, address); [0004] NOP; [0005] NOP; [0006] NOP; [0007] NOP; [0008] NOP; [0009] LOAD(data, address); [0010] … [0011] In order to insert a certain delay in the operation of reading and writing data, several NOP instructions are artificially inserted, which will bring two problems. On...

Claims

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Application Information

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IPC IPC(8): G06F9/30
Inventor 艾方林海波王粟肖佐楠郑茳
Owner 天津国芯科技有限公司
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