Power network design method based on power consumption distribution

A power network and design method technology, applied in computing, electrical digital data processing, instruments, etc., can solve problems such as aggravating the shortage of wiring resources, and achieve the effect of saving software computing time and facilitating changes
CN1987872AInactive Publication Date: 2007-06-27INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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Patent Information

Authority / Receiving Office
CN Β· China
Current Assignee / Owner
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
Publication Date
2007-06-27
Estimated Expiration
Not applicable Β· inactive patent

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Abstract

This invention is about the design technology field for intergrated circuit of ultra large scale, especially the design method for the power source network basing on the distribution of their power loss. It mainly contains five steps. Firstly, the power loss will be estimated in advance according to the turn rate after the layout. Secondly, the network assignment for the power source will be directed by the power loss value according to the previous estimation, and the network metal lay will be confirmed approximately. The width and distance needed by each lay according to the electrical parameter of the metal at various laies. Thirdly, the IR-drop and EM analysis will be carried on to confirm wether the revision assignment is needed or not. Forthly, the accuracy of the power loss value estimated in advance will be tested by the turned documents gained by the test to vector after a suitable optimazation, and meanwile, the need to consummate the design plan for power will be confirmed. Fifthly, the line distribution which is quick and Overall situation will be carried on, a more accurate value with the belt parameters will be gained to test the power loss.
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Description

technical field

[0001] The invention relates to the technical field of very large-scale integrated circuit (VLSI) design, in particular to a design method for quickly constructing a power supply network in back-end design and optimizing it to achieve the best design effect. Background technique

[0002] Today, with the advent of deep sub-micron and nanoscale processes, it is possible to integrate the entire system on a single chip, and the challenges caused by this are rapidly intensifying the difficulty of design. One of them is that as the device density and clock frequency increase, so does the switching current carried by the power and ground nets, which in turn leads to an increase in power density, thus requiring more routing resources to arrange the power nets, and at the same time, As the scale of the chip increases, a large number of wires are caused. Chip area and cost are closely linked. As the area of ​​the chip increases, its manufacturing cost continues to in...

Claims

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