High-k spacer for extension-free CMOS devices with high mobility channel materials

Abstract

A field effect transistor device includes a gate structure formed over a channel region in a semiconductor material. An inner spacer is formed on sidewalls of the gate structure and over an extension region of the semiconductor material. The inner spacer includes charge or dipoles. A source / drain region is formed adjacent to the gate structure. An inversion layer is formed in the extension region induced by the inner spacer to form a conductive link between the channel region and the source / drain region.

Description

BACKGROUND[0001]Technical Field[0002]The present invention relates to high mobility channel devices, and more particularly to devices and methods for forming complementary metal oxide semiconductor (CMOS) devices without extension doping below gate structures.[0003]Description of the Related Art[0004]High mobility channel devices are useful in high speed applications, such as, e.g., communications and high speed computing. Due to their high speed operation, defects in high mobility devices have a larger impact on device function. To ensure proper operation, in one example, low temperature processes (less than 650 degrees C.) need to be employed due to thermal instability of channel materials. The low temperature regimes limit dopant diffusion to / from the channel. In addition, extension dopant processes to extend the channel under spacer structures employ higher temperature implantation steps that may cause collateral damage and undesirable diffusion. Further, if source / drain (S / D) j...

AI Technical Summary

Benefits of technology

This approach eliminates the need for extension doping, preserves high charge mobility, and ensures proper operation by forming a conductive link between channel and source / drain regions, enhancing the reliability and performance of high mobility CMOS devices.

Problems solved by technology

Due to their high speed operation, defects in high mobility devices have a larger impact on device function.

In addition, extension dopant processes to extend the channel under spacer structures employ higher temperature implantation steps that may cause collateral damage and undesirable diffusion.

Further, if source / drain (S / D) junctions are formed with an in-situ doped epitaxial process, it is difficult to link the S / D region to the channel due to the presence of spacer structures, which protect the gate during the epitaxial process.

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