Memory Device And Method For Varying Program State Separation Based Upon Frequency Of Use

a memory device and program state technology, applied in the field of neural networks, can solve the problems of cmos-implemented synapses being too bulky, lack of hardware technology for performance information processing, and mediocre energy efficiency

Active Publication Date: 2020-07-30
SILICON STORAGE TECHNOLOGY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This approach enhances the energy efficiency and computational performance of neural networks by allowing continuous programming and individual tuning of memory cells, making them suitable for high-performance applications while reducing power consumption.

Problems solved by technology

One of the major challenges in the development of artificial neural networks for high-performance information processing is a lack of adequate hardware technology.
However, in addition to high cost, these approaches also suffer from mediocre energy efficiency as compared to biological networks, which consume much less energy primarily because they perform low-precision analog computation.
CMOS analog circuits have been used for artificial neural networks, but most CMOS-implemented synapses have been too bulky given the high number of neurons and synapses.

Method used

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  • Memory Device And Method For Varying Program State Separation Based Upon Frequency Of Use
  • Memory Device And Method For Varying Program State Separation Based Upon Frequency Of Use
  • Memory Device And Method For Varying Program State Separation Based Upon Frequency Of Use

Examples

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Embodiment Construction

[0050]The artificial neural networks of the present invention utilize a combination of CMOS technology and non-volatile memory arrays. Digital non-volatile memories are well known. For example, U.S. Pat. No. 5,029,130 (“the '130 patent”) discloses an array of split gate non-volatile memory cells, and is incorporated herein by reference for all purposes. The memory cell disclosed in the '130 patent is shown in FIG. 2 as memory cell 10. Each memory cell 10 includes source and drain regions 14 / 16 formed in a semiconductor substrate 12, with a channel region 18 there between. A floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and over a portion of the drain region 16. A control gate 22 (i.e., a second, channel controlling gate) has a first portion 22b that is disposed over and insulated from (and controls the conductivity of) a second portion of the channel region 18, and a second portion 22c that extends up ...

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Abstract

A memory device includes a plurality of memory cells and a controller. The controller is configured to program each of the memory cells to one of a plurality of program states, and to read the memory cells using a read operation of applied voltages to the memory cells. During the read operation, separations between adjacent ones of the program states vary based on frequencies of use of the program states in the plurality of memory cells.

Description

RELATED APPLICATIONS[0001]This application claims the benefit of U.S. Provisional Application No. 62 / 798,417, filed Jan. 29, 2019.FIELD OF THE INVENTION[0002]The present invention relates to neural networks.BACKGROUND OF THE INVENTION[0003]Artificial neural networks mimic biological neural networks (the central nervous systems of animals, in particular the brain) which are used to estimate or approximate functions that can depend on a large number of inputs and are generally known. Artificial neural networks generally include layers of interconnected “neurons” which exchange messages between each other. FIG. 1 illustrates an artificial neural network, where the circles represent the inputs or layers of neurons. The connections (called synapses) are represented by arrows, and have numeric weights that can be tuned based on experience. This makes neural nets adaptive to inputs and capable of learning. Typically, neural networks include a layer of multiple inputs. There are typically o...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): G11C16/10G11C16/04G11C16/26G11C14/00G11C11/54G06N3/04H10B41/30H10B69/00
CPCG11C11/54G11C16/26G11C16/10H01L27/11521G11C16/0425G06N3/0454G11C14/00G11C11/5628G11C11/5642G11C16/28G11C16/349G11C16/3495H01L29/42328G06N3/065H10B41/30G06N3/0464G06N3/045G06N3/063H10B69/00
InventorTRAN, HIEU VANLEMKE, STEVENTIWARI, VIPINDO, NHANREITEN, MARK
OwnerSILICON STORAGE TECHNOLOGY