Digital background cancellation of digital to analog converter mismatch noise in analog to digital converters

Abstract

Devices for performing analog-to-digital conversion with reduced noise. In one implementation, an analog-to-digital converter includes at least one internal digital-to-analog converter (DAC) that comprises a plurality of analog components and converts an intermediate digital signal into an associated intermediate analog signal, a dynamic element matching (DEM) circuit coupled to the DAC to permute configurations of the analog components within the DAC, a noise cancellation circuit and a digital subtractor block. The noise cancellation circuit is coupled to receive a first digital sequence comprising a component of a digitized representation of an analog output of the DAC, and a second digital sequence representing a state of the DEM circuitry. The noise cancellation circuit is operable to combine the first and the second digital sequences so as to estimate a digital representation of a DAC noise caused by error sequence introduced mismatches among the analog components within the DAC. The digital subtractor block is coupled to the noise cancellation circuit and operable to use the estimated digital representation of the DAC noise to reduce the DAC noise.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is a continuation (and claims the benefit of priority under 35 USC 120) of U.S. patent application Ser. No. 09 / 792,751 filed Feb. 22, 2001, now U.S. Ser. No. 6,734,818; which claims priority to U.S. Provisional Application No. 60 / 184,205, filed Feb. 22, 2000. The disclosures of the prior applications are considered part of (and are incorporated by reference in) the disclosure of this application.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention generally concerns pipelined analog to digital (A / D) conversion in which is performed noisy digital to analog (D / A) conversion, and pipelined analog to digital (A / D) converters internally incorporating noisy digital to analog (D / A) converters.[0004]The present invention particularly concerns noise, and more particularly noise due to component mismatch, occurring in A / D conversion and in A / D converters—particularly as are used in D / A conversion an...

AI Technical Summary

Benefits of technology

[0010]Pipelined analog-to-digital converters (ADCs) tend to be sensitive to component mismatches in their internal digital-to-analog converters (DACs). These component mismatches give rise to error, referred to as DAC noise, which is not attenuated or canceled along the ADC pipeline as are other types of noise. The present invention contemplates an all-digital technique that significantly mitigates this problem.

[0012]In the presence of realistic component matching limitations, the technique of the present invention improves the overall ADC accuracy by several bits with only moderate digital hardware complexity. Both the measurement and cancellation of DAC noise are entirely performed using digital logic, so no additional analog circuits are required over those of a conventional pipelined. ADC. The digital complexity of the DNC processing is well within practical limits for typical CMOS and BiCMOS circuit technologies.1. Error Correction—Particularly Digital Cancellation of D / A Converter Noise—in Pipelined A / D Converters

[0023]First, an enhancement to the flash DAC of each stage serves to cause the DAC to produce, as well as the DAC digital signal, both random bits and parity bits.

Problems solved by technology

Pipelined analog-to-digital converters (ADCs) tend to be sensitive to component mismatches in their internal digital-to-analog converters (DACs).

These component mismatches give rise to error, referred to as DAC noise, which is not attenuated or canceled along the ADC pipeline as are other types of noise.

The digital complexity of the DNC processing is well within practical limits for typical CMOS and BiCMOS circuit technologies.

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