TB-RM circuit logic detection method, storage medium and equipment

Abstract

The invention relates to a TB-RM circuit logic detection method, a storage medium and equipment. The method comprises the following steps: reading a Boolean logic circuit to be detected; any k variable logic function is extracted, and whether the k variable logic function meets RM logic general judgment conditions or not is judged; when the RM logic general judgment condition is met, traversing a multivariable parent layer structure and a variable quantum layer structure layer by layer, and performing positive / inverse variable condition judgment on each layer of structure; and obtaining a logic judgment result, and determining a logic function representation mode suitable for the to-be-detected circuit according to the logic judgment result. Compared with the prior art, the method has the advantages that the logic detection efficiency can be improved while the logic detection accuracy is ensured, and the like.

Description

Technical Field

[0001] The present invention relates to the technical field of TB-RM (Traditional Boolean and Reed-Muller) logic circuit optimization, and in particular to a TB-RM circuit logic detection method, storage medium and device. Background Art

[0002] Early IC design focused on Boolean logic. In fact, digital circuits can also be implemented through RM (Reed-Muller) logic based on XNOR / XOR (exclusive or / exclusive OR) operations, which can realize complete logical functions. Studies have shown that digital circuits using RM-based logic (such as arithmetic logic circuits, parity check circuits, etc.) have more advantages than traditional Boolean logic in terms of power consumption, area, speed and testability. Existing EDA (Electronic Design Automation) software is almost all based on TB (Traditional Boolean) logic to design circuits, which makes it impossible for circuits suitable for RM logic to achieve performance optimization at the logic level, thereby limiting the improvement of circuit performance. On the contrary, if RM logic is used to comprehensively optimize circuits suitable for TB logic, it will make the circuit expression more cumbersome, the circuit structure more complex, and reduce circuit performance. For most circuits, the TB-RM dual logic optimization scheme combining RM logic with TB logic can significantly improve circuit performance. However, the current research on logic detection methods is still in its infancy, and the relevant theories are not yet mature. The growth of integrated circuit scale, complexity and integration has greatly increased the complexity of logic circuit structure. In addition, truth tables, Karnaugh maps and description forms based on the sum-of-products paradigm are not conducive to reflecting circuit details and analyzing circuits, and have low efficiency in operating logic functions. In addition, existing research only combines the XOR operation basis with TB logic for single-variable synthesis, and does not fully consider the XNOR operator and multi-variable synthesis. Therefore, in front-end design, it is necessary to quickly analyze which nodes are suitable for XOR / XNOR logic synthesis and which nodes are suitable for TB logic synthesis.

[0003] For the existing large-scale circuit optimization field, it is urgent to study an effective logic synthesis method. Summary of the invention

[0004] The purpose of the present invention is to overcome the defects of the above-mentioned prior art and to provide a TB-RM circuit logic detection method, storage medium and device with high accuracy and high detection efficiency.

[0005] The purpose of the present invention can be achieved by the following technical solutions:

[0006] A TB-RM circuit logic detection method comprises the following steps:

[0007] Read the Boolean logic circuit to be detected;

[0008] Extract any k-variable logic function and determine whether the k-variable logic function satisfies the general judgment condition of RM logic;

[0009] When the general judgment condition of the RM logic is met, the logic function MROBDD traverses the multi-variable parent layer structure and the multi-variable child layer structure layer by layer, and performs positive / negative variable condition judgment on each layer structure;

[0010] A logic judgment result is obtained, and a logic function representation method applicable to the circuit to be detected is determined according to the logic judgment result.

[0011] Furthermore, the general judgment condition of the RM logic is expressed as:

[0012]

[0013] Among them, f(x1,x2,...,x k ) is a k-variable logistic function, parent (1) ,parent (2) ,…,parent (n) Represents the parent node group, child (1) ,child (2) ,…,child (m) Represents a child node group, which is divided into low-edge child nodes child L(j) and high edge child R(j) , x parent(i) For the node parent (i) Function of variable, x child-L(j) For the node child L(j) Function of variable, x child-R(j) For the node child R(j) The variable function, f L (x1,x2,...,x k ), f R (x1,x2,...,x k ) indicates a pointer to a node or function.

[0014] Furthermore, the layer-by-layer traversal is specifically as follows:

[0015] Starting from the 0th layer where the root node of the logic function MROBDD is located, the positive / negative variable judgment of the variable parent layer structure and the multi-variable child layer structure is performed layer by layer.

[0016] Furthermore, the positive / negative variable conditions of the multivariate parent layer structure are specifically:

[0017] There exists parent(i+1)=low[parent(i)], such that

[0018]

[0019] where i∈[1,…,n], low[parent] and high[parent] represent the non-terminal left and right child nodes in the parent structure, parent(i) represents the i-th parent node, and x parent(i) In terms of inverse variables, x parent(i) For the node parent (i) Variable function, child L(1) Represents a low-edge child node.

[0020] Furthermore, the positive / negative variable conditions of the multivariable sub-layer structure are specifically:

[0021] Child exists L(j+1) =low[child L(j) ], child R(j+1) =low[child R(j) ], so that

[0022]

[0023] where j∈[1,…,m], low[child] and high[child] represent the non-terminal left and right child nodes in the sublayer structure, and x child(j) In terms of inverse variables, x child(j) For the node child (j) Variable function, child L(j) 、child R(j) Represents a child node.

[0024] Furthermore, the logic function representation includes RM logic representation, TB logic representation and TB-RM logic representation.

[0025] Furthermore, determining the logic function representation mode applicable to the circuit to be detected according to the logic judgment result specifically includes:

[0026] If, except for the layer with only one "low" edge pointing to the "0" terminal node, the positive / negative variable conditions of the multivariable parent layer structure and the positive / negative variable conditions of the multivariable child layer structure are met between two adjacent layers, then the logic function of the circuit to be detected is suitable for being represented by RM logic;

[0027] If the above conditions are not met between two adjacent layers, the logic function of the circuit to be detected is suitable for TB logic representation;

[0028] If there are some adjacent layers that meet the above conditions, the logic function of the circuit to be detected is suitable for being represented by TB-RM logic.

[0029] Furthermore, when the TB-RM logic representation is adopted, the number of nodes of the TB-RM logic function is represented by calculating the number of all operation bases after the logic detection.

[0030] The present invention also provides a computer-readable storage medium, comprising one or more programs for execution by one or more processors of an electronic device, wherein the one or more programs include instructions for executing the TB-RM circuit logic detection method as described above.

[0031] The present invention also provides an electronic device, comprising one or more processors, a memory and one or more programs stored in the memory, wherein the one or more programs include instructions for executing the TB-RM circuit logic detection method as described above.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] (1) Optimization of the logic level in integrated circuit design can often reduce the area of ​​the integrated circuit. Logic detection is to determine which logic is suitable for the circuit to be implemented and output the optimal expression, thereby improving the quality of circuit design. It cannot be ignored in the optimization of logic circuits. Existing logic detection methods for large-scale circuits have limitations (only suitable for small-scale logic circuits) or low efficiency. Therefore, what is most needed at present is to find a logic detection method that can quickly and accurately detect large-scale logic circuits. By analyzing and detecting the MROBDD of the logic function based on the characteristics of multi-variable XOR logic and multi-variable XNOR logic, it can be determined whether the RM logic synthesis part of a function is suitable for logic synthesis based on OR / XNOR logic, AND / XOR, or a combination of the two. It can also identify and determine the logic synthesis suitable for multi-variable RM logic synthesis, thereby improving the accuracy of the MROBDD-based logic detection method.

[0034] (2) Using the simplest MROBDD to describe the logic function can improve the efficiency of the operation of the logic function, thereby improving the efficiency of logic detection. Starting from the characteristics of multi-variable XOR logic and multi-variable XNOR logic, the logic function is analyzed and detected directly according to the characteristics of RM logic, which can improve the efficiency of logic detection while ensuring the accuracy of logic detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1It is a schematic diagram of the process of the present invention;

[0036] Figure 2 Schematic diagram of the multivariable RM logic structure in an embodiment of the present invention. DETAILED DESCRIPTION

[0037] The present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. This embodiment is implemented based on the technical solution of the present invention, and provides a detailed implementation method and specific operation process, but the protection scope of the present invention is not limited to the following embodiments.

[0038] like Figure 1 As shown, this embodiment provides a TB-RM circuit logic detection method, comprising the following steps:

[0039] Step 1, read the Boolean logic circuit.

[0040] Step 2: Perform a general judgment on any k-variable logic function.

[0041] The nodes of the MROBDD (Multi-valued Reduced Ordered Binary Decision Diagram) of the RM logic relationship can correspond to the identities of "parent" and "child" respectively, so the k-variable logic function f(x1,x2,…,x k ) must have a parent node group parent (1) ,parent (2) ,…,parent (n) and the "child" node group child (1) ,child (2) ,…,child (m) , the child node group can be divided into low-edge child nodes child L(j) and high edge child R(j) , where m∈N * ,n∈N * ,m+n=k.

[0042] In this step, a general RM logic judgment is performed on any k-variable logic function, such as Figure 2 As shown, the general judgment condition is expressed as:

[0043]

[0044] If the above formula is satisfied, the final point is the same point node or function f L (x1,x2,...,x k ) and f R (x1,x2,...,xk ), that is, f L and f R , then parent (1) ,parent (2) ,…,parent (n) and child (1) ,child (2) ,…,child (m) There is an RM logical relationship between them. parent(i) For the node parent (i) Function of variable, x child-L(j) For the node child L(j) Function of variable, x child-R(j) For the node child R(j) Function of variable, x fL f L (x1,x2,...,x k ), that is, node f L Function of variable, x fR f R (x1,x2,...,x k ), that is, node f R Function of variable, x fL ≠x fR The logical function expression of RM logic universal judgment is as follows:

[0045]

[0046] Step 3: Perform positive / negative variable judgment on the multivariate parent layer structure.

[0047] The positive / negative variable judgment of the multivariable parent layer structure is expressed as: Under the general judgment condition of step 2, if parent(i+1)=low[parent(i)], then

[0048]

[0049] Where i∈[1,…,n], low[parent] and high[parent] represent the non-terminal left and right child nodes in the parent structure, which are low edges and high edges respectively. When the above equation is satisfied, that is, the high edge of parent(i) points to child L(1) , then x parent(i) Expressed as an inverse variable.

[0050] Step 4: Perform positive / negative variable judgment on the multivariate sub-layer structure.

[0051] The positive / negative variable judgment of the multivariate sub-layer structure is expressed as: Under the general judgment condition of step 2, if the child L(j+1) =low[child L(j) ], child R(j+1) =low[child R(j) ], so that

[0052]

[0053] Where j∈[1,…,m], low[child] and high[child] represent the non-terminal left and right child nodes in the sub-layer structure. When the above equation is satisfied, that is, one of the child L(j) The high edge of the node points to f L , and satisfies one of the children R(j) The high edge of the node points to f R , then x child(j) Expressed as an inverse variable.

[0054] Finally, the multivariable RM logic function expression is as follows:

[0055]

[0056] Step 5, output the logical judgment results of the binary decision diagram layer by layer by using the classic pre-order traversal method, that is, the node variables.

[0057] In this step, starting from the 0th layer where the root node of the logic function MROBDD is located, it is verified layer by layer whether there are conditions that meet the general judgment, the conditions that meet the multivariable parent layer structure, and the conditions that meet the multivariable child layer structure between the two adjacent layers. If the two adjacent layers in the decision diagram meet the above conditions except for the layer with only one "low" edge pointing to the "0" terminal node, then the logic function is suitable for RM logic representation; if the two adjacent layers do not meet the above conditions, then the logic function is suitable for TB logic representation; if there are some adjacent layers that meet the above conditions, then the logic function is suitable for TB-RM logic representation.

[0058] Finally, the dual logic function of the test circuit is output based on the pre-order traversal and logic detection results of the MROBDD. Here, the number of nodes of the TB-RM logic function is represented by calculating the number of all operation bases after logic detection.

[0059] If the above method is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0060] In another embodiment, an electronic device is provided, comprising one or more processors, a memory and one or more programs stored in the memory, wherein the one or more programs include instructions for executing the TB-RM circuit logic detection method as described above.

[0061] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0062] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0063] The preferred specific embodiments of the present invention are described in detail above. It should be understood that a person skilled in the art can make many modifications and changes based on the concept of the present invention without creative work. Therefore, any technical solution that can be obtained by a person skilled in the art through logical analysis, reasoning or limited experiments based on the concept of the present invention on the basis of the prior art should be within the scope of protection determined by the claims.

Claims

1. A TB-RM circuit logic detection method, characterized in that: The following steps are involved: Read the Boolean logic circuit to be detected; Extract any k-variable logic function and determine whether the k-variable logic function satisfies the general judgment condition of RM logic; When the general judgment condition of the RM logic is met, the logic function MROBDD traverses the multi-variable parent layer structure and the multi-variable child layer structure layer by layer, and performs positive / negative variable condition judgment on each layer structure; A logic judgment result is obtained, and a logic function representation method applicable to the circuit to be detected is determined according to the logic judgment result.

2. The TB-RM circuit logic detection method according to claim 1, characterized in that: The general judgment condition of the RM logic is expressed as: Among them, f(x1,x2,...,x k ) is a k-variable logistic function, parent (1) ,parent (2) ,…,parent (n) Represents the parent node group, child (1) ,child (2) ,…,child (m) Represents a child node group, which is divided into low-edge child nodes child L(j) and high edge child R(j) , x parent(i) For the node parent (i) Function of variable, x child-L(j) For the node child L(j) Function of variable, x child-R(j) For the node child R(j) The variable function, f L (x1,x2,...,x k ), f R (x1,x2,...,x k ) indicates a pointer to a node or function.

3. The TB-RM circuit logic detection method according to claim 1, characterized in that: The layer-by-layer traversal is specifically as follows: Starting from the 0th layer where the root node of the logic function MROBDD is located, the positive / negative variable judgment of the variable parent layer structure and the multi-variable child layer structure is performed layer by layer.

4. The TB-RM circuit logic detection method according to claim 1, characterized in that: The positive / negative variable conditions of the multivariate parent layer structure are specifically: There exists parent(i+1)=low[parent(i)], such that where i∈[1,…,n], low[parent] and high[parent] represent the non-terminal left and right child nodes in the parent structure, parent(i) represents the i-th parent node, and x parent(i) In terms of inverse variables, x parent(i) For the node parent (i) Variable function, child L(1) Represents a low-edge child node.

5. The TB-RM circuit logic detection method according to claim 1, characterized in that: The positive / negative variable conditions of the multivariable sub-layer structure are specifically: Child exists L(j+1) =low[child L(j) ], child R(j+1) =low[child R(j) ], so that where j∈[1,…,m], low[child] and high[child] represent the non-terminal left and right child nodes in the sublayer structure, and x child(j) In terms of inverse variables, x child(j) For the node child (j) Variable function, child L(j) 、child R(j) represents the child node, f L 、f R Indicates pointing to a node.

6. The TB-RM circuit logic detection method according to claim 1, characterized in that: The logic function representation includes RM logic representation, TB logic representation and TB-RM logic representation.

7. The TB-RM circuit logic detection method according to claim 6, characterized in that: Determining the logic function representation mode applicable to the circuit to be detected according to the logic judgment result specifically includes: If, except for the layer with only one "low" edge pointing to the "0" terminal node, the positive / negative variable conditions of the multivariable parent layer structure and the positive / negative variable conditions of the multivariable child layer structure are met between two adjacent layers, then the logic function of the circuit to be detected is suitable for being represented by RM logic; If the above conditions are not met between two adjacent layers, the logic function of the circuit to be detected is suitable for TB logic representation; If there are some adjacent layers that meet the above conditions, the logic function of the circuit to be detected is suitable for being represented by TB-RM logic.

8. The TB-RM circuit logic detection method according to claim 6, characterized in that: When the TB-RM logic representation is adopted, the number of nodes of the TB-RM logic function is represented by calculating the number of all operation bases after the logic detection.

9. A computer-readable storage medium, characterized in that: It comprises one or more programs for execution by one or more processors of an electronic device, wherein the one or more programs comprise instructions for executing the TB-RM circuit logic detection method as claimed in any one of claims 1 to 8.

10. An electronic device, characterized in that: The system comprises one or more processors, a memory and one or more programs stored in the memory, wherein the one or more programs include instructions for executing the TB-RM circuit logic detection method according to any one of claims 1 to 8.

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