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Method for improving code parallelism degree and implementing coding delay

A coding and delay technology, applied in coding, coding components, error correction/detection using block codes, etc., can solve problems such as unsuitable for expansion

Inactive Publication Date: 2009-05-13
PANASONIC CORP
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Problems solved by technology

Therefore, from this point of view, this method is obviously not suitable for extending to lower bit rates

Method used

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  • Method for improving code parallelism degree and implementing coding delay
  • Method for improving code parallelism degree and implementing coding delay
  • Method for improving code parallelism degree and implementing coding delay

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Embodiment Construction

[0043] Embodiments of the present invention will be described in detail below with reference to the accompanying drawings, and unnecessary details and functions for the present invention will be omitted during the description to prevent confusion in the understanding of the present invention.

[0044] In this embodiment, an LDPC parity check matrix with a double-diagonal structure is taken as an example for description. Figure 9 It shows a schematic diagram of extending the double-diagonal structure quasi-cyclic LDPC code with a medium code rate of 1 / 2 as a base code to 1 / 3 and 1 / 4 code rates. It can be assumed that the size of the base matrix is ​​m*n. Here, as an example, where m=6, n=12. Figure 9 The upper left box of the extended matrix shown is the base matrix. Such as Figure 9 As shown, the base matrix is ​​a matrix of order 6×12.

[0045] In order to extend the base matrix, the code rate of the spread code can be set to 1 / k (k=3, 4, 5...k0), where 1 / k0 is the min...

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Abstract

The invention discloses a coding delay method for reducing double diagonal quasi-cyclic low density parity check code, comprising the steps: based on the set extended code rate of 1 / k, the double diagonal of basis matrix at the m line and n row can be extended along the direction of the double diagonal to form an expended matrix of the double diagonal structure, wherein, k is equal to 3, 4, 5...k0, and 1 / k0 is the minimum code rate; a first nonzero element of the i*m+1line check part is moved towards left direction to (n-m+l) line along the i*m+1line, wherein, i is equal to 1, 2, ..., k0-1; a first check relation is taken as initiation factor to calculate check bit of n-m+l row; by utilizing the check relation of moving towards left direction to (n-m+l) line, a plurality of groups of check bits are calculated in parallel by a mode of recursive coding.

Description

technical field [0001] The present invention relates to a method for reducing encoding time delay by increasing encoding parallelism, in particular, it involves introducing multiple encoding parallelisms to double-diagonal quasi-cyclic low-density parity-check (LDPC) codes, so that the extended The encoding time of the code is approximately the same as that of the base code, and will not increase linearly with the reduction of the code rate. Background technique [0002] In recent years, wireless communication systems are being developed to be able to transmit data at very high speeds. For this reason, a more efficient coding scheme than that of the prior art is required. Low Density Parity-Check Code (LDPC Code) is a powerful forward error correction coding method rediscovered in the past decade. Under the condition of long code construction, LDPC code has approached the Shannon limit, so it is considered to be an effective replacement technology for Turbo code, and it is...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/11
CPCH03M13/6393H03M13/116H03M13/1188
Inventor 陈超江浩徐明栗谦一西尾昭彦
Owner PANASONIC CORP
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