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Galois field multiplying unit realizing device

A multiplier and multiplication technology, applied in the field of information security, can solve problems such as high computing speed, lack of reach, and high complexity, and achieve the effect of improving computing speed

Inactive Publication Date: 2010-02-17
BEIJING UNIV OF POSTS & TELECOMM
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

However, the current algorithms and optimization methods are relatively complex to implement, and cannot achieve high calculation speed.

Method used

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Embodiment Construction

[0026] Attached below figure 1 The present invention will be described in detail.

[0027] In the first step, the form of reducible polynomial is P(x)=x m +x kt +...+x k2 +x k1 +1, and satisfy the condition of 1≤k1<k2<...<kt≤m / 2, calculate the Q matrix according to the following algorithm:

[0028] The 0th row of the Q matrix has t+1 1s, and the 1s are distributed in the 0, k1, k2, ..., kt columns respectively.

[0029] Row 1 to row m-kt-1 of the Q matrix are obtained by sequentially shifting right from row 0.

[0030] The construction rules of the m-kt to m-2 rows of the Q matrix are as follows:

[0031] When the last column of row i ends with 1, row i+1 is shifted one bit to the right and XORed with the value of row 0;

[0032] When the last column of row i ends with 0, row i+1 is shifted one bit to the right.

[0033] The Q matrix can be obtained through the above algorithm. The Q matrix generation module can be constructed through the Q matrix. The Q matrix genera...

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Abstract

The invention discloses a Galois field multiplying unit realizing device which converts the calculation of Galois field multiplication into the multiplication of matrix modules. The Galois field multiplying unit realizing device comprises an L matrix module, a U matrix module, an m-bit data input / output interface, a Q matrix generating module and the like. The structure of the Galois field multiplying unit realizing device relates to a 3m-1 group of binary and gate trees and one group of exclusive or gate trees. The embodiment of the invention provides an example for realizing a Galois field GF (2<128>) multiplying unit on a basis of an FPGA when m=128. The multiplying unit can be used for the hardware realization of a G-hash function and can achieve a calculation speed of over 10Gbps.

Description

technical field [0001] The invention relates to a device for realizing a Galois field multiplier, which belongs to the technical field of information security, and specifically relates to a device based on a reducible polynomial whose form is P(x)=x m +x kt +...+x k2 +x k1 +1, where 1≤k1<k2<...<kt≤m / 2 m-bit Galois field multiplier device. Background technique [0002] Finite field multiplication is an operation that is widely used in the field of cryptography at present, and many encryption authentication algorithms use finite field multiplication. Galois field is an important finite field, and a Galois field operation refers to two types of operations performed under specific rules: addition and multiplication. Among them, the Galois field GF(2) only contains two elements 0 and 1, the addition operation can be easily realized by using an exclusive OR gate, and its multiplication can also be easily realized by using an AND gate. In particular, when the Galois f...

Claims

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Application Information

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IPC IPC(8): G06F7/72
Inventor 寿国础胡怡红宁帆郭志刚霍甲屈善新陆阳高泽华钱宗珏
Owner BEIJING UNIV OF POSTS & TELECOMM
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