Replacement device and method for chip shared cache and corresponding processor

Abstract

The invention provides a replacement device and a replacement method for a chip shared cache and a corresponding processor. The device comprises a local scoring module and a replacement selection module, wherein the local scoring module comprises a plurality of scoring registers, and the scoring registers are used for storing cache block addresses and scores of the cache block addresses; the local scoring module is used for scoring an access address and an address corresponding to the cached data, and updating the cache block addresses stored in the scoring registers and the scores of the cache block addresses; and the replacement selection module is used for bypassing the access address under the condition that the score of the access address is lowest, otherwise, replacing the data corresponding to the address of the cached data with lowest score by using the data corresponding to the access address. Serious jitter of the shared cache in a multi-core / many-core processor is solved, and the share cache is better utilized.

Description

technical field [0001] The invention relates to the field of computer chips, in particular to multi-core or many-core processors. Background technique [0002] In the past few years, due to the limitations of instruction-level parallelism, power consumption, and chip temperature, mainstream chip manufacturers have shifted from producing single-core chips to producing multi-core or many-core chips. The design of multi-core or many-core chips faces many challenges that did not exist in the single-core era, one of which is the design of on-chip shared high-speed cache (cache). At present, there are two different methods for multi-core / many-core cache design: [0003] 1 Private cache: Each small core has a private cache. The advantage of this method is that the small cores are isolated from each other, and the behavior of one small core will not affect the performance of other small cores; the disadvantage is that the on-chip storage cannot be effectively used, especially when...

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Problems solved by technology

Although the sharing of the last-level cache by multiple small cores provides convenience for data transfer between small cores, it also causes some problems: although each small core has strong temporal and spatial locality in accessing the shared cache , but the spatiotemporal locality of the sum of many small core accesses is poor

But when figure 2 In the access sequence of , the cache block containing address A0 will be frequently replaced out of the cache, and the number of accesses to address A0 will be cleared every time it is replaced, which makes the LFU strategy unable to accumulate enough accesses for address A0 , so that the LFU strategy cannot solve figure 2 The jitter problem shown

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