Method for manufacturing complementary metal oxide semiconductor device structure

Abstract

The invention discloses a method for manufacturing a complementary metal oxide semiconductor (CMOS) device structure. The method comprises the following steps: providing a first front-end device structure comprising a substrate and a grid insulation layer, wherein the substrate is divided into a first region containing a P well and a second region containing an N well, and forming an N-type covering layer and a metal barrier layer in sequence on the upper surface of the grid insulation layer; then removing the metal barrier layer and the N-type covering layer corresponding to the second region; forming P-type covering layers above the first region and the second region; and removing a P-type covering layer corresponding to the first region by adopting a mask-shielding mode; obtaining a second front-end device structure, and further preparing the CMOS device structure provided with a first grid structure and a second grid structure on the second front-end device structure. The CMOS device structure prepared by the method disclosed by the invention preferably meets the actual technological requirements and the product yield can be improved.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a method for manufacturing a complementary metal oxide semiconductor device structure. Background technique [0002] With the continuous development of semiconductor manufacturing technology, the line width of the gate, which is used to measure the process level of semiconductor manufacturing technology, is also getting smaller and smaller. At present, the line width of the gate has been able to reach 65nm or even smaller. A small gate line width can reduce the driving voltage of the formed semiconductor device, thereby reducing power consumption. In addition, the small gate line width can also reduce the size of the formed semiconductor device, improve the integration level, increase the number of semiconductor devices per unit area, and reduce the cost. Therefore, how to prepare a gate structure with a smaller line width has become a current research hotspot. [0003]...

AI Technical Summary

Problems solved by technology

Conversely, when the P-type cladding layer is deposited first on the substrate, and then the N-type cladding layer is deposited, the thickness of the second P-type cladding layer 105B may be lost, thereby failing to obtain a satisfactory CMOS device structure

Further, the leakage current of the CMOS device structure prepared by the above method increases, and the threshold voltage decreases

Images