Digital satellite interface bias verification system

Abstract

The invention relates to a digital satellite interface bias verification system, which comprises a clock module, an upper computer interface module, an FPGA (field programmable gate array), a satellite-mounted interface module and a power supply module. The power supply module is used for supplying power to the upper computer interface module, the FPGA and the satellite-mounted interface module, the clock module is used for providing clock signals for the FPGA, the upper computer interface module is used for realizing data exchange and transmission between the FPGA and an upper computer, and the satellite-mounted interface module is used for realizing data exchange and transmission between the FPGA and a satellite-mounted device and biasing a rising edge and a falling edge of a time sequence signal output by the FPGA; and the FPGA is used for realizing data interaction and delay bias of the time sequence signal. The time sequence bias of digital signals can be achieved, the delay of different digital signals is produced by the FPGA, and the working conditions of the digital interface of the satellite can be tested to obtain the time sequence tolerance. Moreover, real-time changes in the rising edge and the falling edge of signals can be realized through a variable resistance and capacitance network.

Description

technical field [0001] The invention relates to a satellite digital interface deviation verification system, which is suitable for verification of the input and output characteristics of the satellite digital interface. Background technique [0002] At present, many digital transmission interfaces are used in domestic high-orbit communication satellite measurement and control subsystems, which are used to transmit telemetry signals and remote control commands between different stand-alone machines. [0003] High-orbit communication satellites mainly use serial interfaces to realize digital signal transmission, and data signals are transmitted according to the specified timing and level. A more commonly used transmission form is: the telemetry acquisition terminal outputs a strobe signal and a clock signal, and the acquired terminal outputs serial telemetry data shifted according to the clock signal after the strobe signal arrives. For the telemetry acquisition end, it is ne...

AI Technical Summary

Problems solved by technology

But the system mainly has the following three problems: 1. The delay relationship of multiple digital signals cannot be set; 2. The rising edge and falling edge of the signal depend on the characteristics of the selected chip and cannot be adjusted; 3. Mainly for the function Test, unable to grasp the tolerance characteristics of the interface

Therefore, during the entire satellite test phase of the satellite, when the temperature or the length of the connecting cable changes, the performance of the interface will change, and the phenomenon of interface timing mismatch will occur from time to time

[0005] Since the previous digital interface verification system can only complete the functional test without comprehensive test verification of the interface performance, it can no longer meet the development needs of the current satellite platform digital interface test verification

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