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Superblock management method, memory device and controller of memory device

A memory device, superblock technology, applied in the direction of memory address/allocation/relocation, etc., can solve the problems of poor sequential reading performance and inability to guarantee channel bandwidth, etc.

Active Publication Date: 2012-05-30
SILICON MOTION TECH CORP
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AI Technical Summary

Problems solved by technology

For example: the management mechanism of the related technology cannot guarantee the channel bandwidth of each channel in a flash memory with multiple channels; another example: the performance of the related technology for sequential reading after random writing is very poor

Method used

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  • Superblock management method, memory device and controller of memory device
  • Superblock management method, memory device and controller of memory device
  • Superblock management method, memory device and controller of memory device

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Embodiment Construction

[0053] Please refer to Figure 1A , Figure 1A It is a schematic diagram of a memory device 100 according to a first embodiment of the present invention. The memory device 100 of this embodiment can be a portable memory device (for example, memory that conforms to SD / MMC, CF, MS, XD standards). Card), or solid state drive (SSD, Solid State Drive). The memory device 100 includes: a flash memory (Flash Memory) 120 including at least one information block (Block) 120B; and a controller for accessing the flash memory 120, wherein the controller is, for example, a memory controller 110. According to this embodiment, the memory controller 110 includes a microprocessor 112, a read only memory (ROM) 112M, a control logic 114, at least one buffer memory 116, and an interface logic 118. In addition, the read-only memory 112M of this embodiment is used to store a program code 112C, and the microprocessor 112 is used to execute the program code 112C to control access to the flash memory 120...

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Abstract

The invention relates to a superblock management method applied to a controller of a flash memory with a plurality of channels, wherein the flash memory comprises a plurality of blocks respectively corresponding to the channels. The method comprises the following steps of: storing block grouping relationships corresponding to a plurality of superblocks by utilizing a superblock mapping table, wherein blocks in each superblock respectively correspond to the channels; and when a specific block corresponding to a specific channel in a superblock is detected to have no remained writing-in space, utilizing at least one blank block corresponding to the specific channel in at least one other superblock as the extension of the specific block for next writing-in according to the superblock mapping table. According to the superblock management realized by the invention, the whole channel bandwidth of the flash memory with the plurality of channels can be increased; and the aim of giving consideration to both operation efficiency and control and management on the use of a system resource can be achieved under the condition that the chip area and the relevant cost are not greatly increased.

Description

Technical field [0001] The present invention relates to access to a flash memory (Flash Memory) with multiple channels, and more specifically, to a method for managing a meta block (Meta Block) and a related memory device and its controller . Background technique [0002] In recent years, due to the continuous development of flash memory technology, various portable memory devices (such as memory cards that meet SD / MMC, CF, MS, and XD standards) or solid state drives (SSD) with flash memory have been widely used It is implemented in many applications. Therefore, the access control of the flash memory in these memory devices has become a very hot topic. [0003] In terms of commonly used NAND flash memory, it can be mainly divided into two types of flash memory, single level cell (SLC) and multiple level cell (MLC). Each transistor used as a memory cell in a single-level cellular flash memory has only two charge values, which are used to represent logic value 0 and logic value 1....

Claims

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Application Information

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IPC IPC(8): G06F12/02
Inventor 沈扬智
Owner SILICON MOTION TECH CORP
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