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Block management method, memory device and controller of memory device

A technology of memory device and controller, applied in the direction of memory address/allocation/relocation, etc., can solve the problems of poor sequential reading performance, inability to guarantee channel bandwidth, etc., and achieve the effect of improving channel bandwidth

Active Publication Date: 2012-05-30
SILICON MOTION TECH CORP
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  • Abstract
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  • Application Information

AI Technical Summary

Problems solved by technology

For example: the management mechanism of the related technology cannot guarantee the channel bandwidth of each channel in a flash memory with multiple channels; another example: the performance of the related technology for sequential reading after random writing is very poor

Method used

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  • Block management method, memory device and controller of memory device
  • Block management method, memory device and controller of memory device
  • Block management method, memory device and controller of memory device

Examples

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Embodiment Construction

[0047] Please refer to Figure 1A , Figure 1A It is a schematic diagram of a memory device 100 according to a first embodiment of the present invention, wherein the memory device 100 of this embodiment is especially a portable memory device (for example: a memory card conforming to SD / MMC, CF, MS, XD standards ), or solid state drive (SSD, Solid State Drive), etc. The memory device 100 includes: a flash memory (Flash Memory) 120 ; and a controller for accessing the flash memory 120 , wherein the controller is, for example, a memory controller 110 . According to this embodiment, the memory controller 110 includes a microprocessor 112 , a read only memory (ROM) 112M, a control logic 114 , at least one buffer memory 116 , and an interface logic 118 . In addition, the ROM 112M of this embodiment is used to store a program code 112C, and the microprocessor 112 is used to execute the program code 112C to control access to the flash memory 120 . Please note that the program code 11...

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Abstract

The invention relates to a block management method applied to a controller of a flash memory with a plurality of channels, wherein the flash memory comprises a plurality of blocks respectively corresponding to the channels. The method comprises the following steps of: obtaining at least one part of a plurality of address-to-channel mapping relationships for writing-in operation; and writing at least one page of data into the flash memory through at least one channel in a page mode according to at least one of the address-to-channel mapping relationships. The invention also provides a relevant memory device and a controller thereof. According to the management realized by the invention, the whole channel bandwidth of the flash memory with the plurality of channels can be increased; in addition, the problem that a certain channel is excessively used does not exist, and compared with a relevant technology, the block management method can be used for achieving the aim of giving consideration to both operation efficiency and control and management on the use of a system resource under the condition that the chip area and the relevant cost are not greatly increased.

Description

technical field [0001] The present invention relates to the access (Access) of flash memory (Flash Memory) with multiple channels, and more specifically, relates to a method for block management, a related memory device and its controller. Background technique [0002] In recent years, due to the continuous development of flash memory technology, various portable memory devices (for example: memory cards conforming to SD / MMC, CF, MS, XD standards) or solid state drives (Solid State Drive, SSD) with flash memory are widely used implemented in many applications. Therefore, the access control of the flash memory in these memory devices has become a very hot topic. [0003] As far as the commonly used NAND flash memory is concerned, it can be mainly divided into two types of flash memory: single level cell (Single Level Cell, SLC) and multiple level cell (Multiple Level Cell, MLC). Each transistor in the single-level cell flash memory, which is regarded as a memory unit, has o...

Claims

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Application Information

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IPC IPC(8): G06F12/06
Inventor 张敬勤周柏升沈扬智
Owner SILICON MOTION TECH CORP
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