Counter control type delay-locked loop circuit with mistaken locking correction mechanism

Abstract

The invention relates to a counter control type delay-locked loop (DLL) circuit with a mistaken locking correction mechanism. The circuit comprises a digital delay line, a phase discriminator, an addition / subtraction counter and a clock phase arithmetic circuit. An input reference clock signal CLK is connected to the digital delay line and the phase discriminator respectively. The output of the digital delay line is connected to the phase discriminator and the clock phase arithmetic circuit. The output of the phase discriminator is connected to the input of the addition / subtraction counter. The output of the addition / subtraction counter is connected to the digital delay line. Whether the delay of a delayed output clock signal is consistent with a locking condition or not is judged through a locking process detection window, and the delay is timely regulated according to a detection result, so that mistaken locking is avoided, and a delay locking function is accurately realized. The circuit has the advantages that: the problem that the conventional DLL structure is easily mistakenly locked is effectively solved; moreover, the circuit has a wide frequency range and much phase output; and the yield of a chip can be improved.

Description

technical field [0001] The invention relates to a digital delay-locked loop circuit, in particular to a counter-controlled delay-locked loop circuit with an error locking correction mechanism. Background technique [0002] Phase-locked loop (PLL) and delay-locked loop (DLL) are widely used in large-scale integrated circuits to solve the problem of clock skew and adjust the delay of the clock signal. Compared with PLL, DLL has more advantages. It is a first-order system with good stability, shorter lock time, simple design, no jitter accumulation, etc., so DLL has gradually become the clock signal for delay adjustment. mainstream circuit. [0003] DLLs can be categorized as Analog DLLs, Digital DLLs, and Mixed-Mode DLLs. Analog DLLs and mixed-mode DLLs are more resistant to clock jitter and clock skew, but this also limits the frequency range. In addition, the analog DLL requires a longer lock time and a larger chip area, and the sensitivity of the analog circuit also make...

AI Technical Summary

Problems solved by technology

2) The counter controls the DLL; it replaces the register in the first category with a counter, thereby reducing the hardware of the controller, but its lock time and the number of required delay units are similar to the first category

3) Successive approximation DLL; successive approximation DLL can shorten the locking time through binary search algorithm, but its frequency range is relatively narrow

Since there is no detection mechanism in the locking process, only the input signal CLK is compared with the final delayed output signal CK N phasing situation, it is not possible to determine when the lock is complete when the CK N Whether the delay is in the range of meeting the locking conditions, so it is possible to form a wrong lock

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