Method and system for testing board card

Abstract

The invention suitable for the technical field of computers provides a method and a system for testing a board card. The method comprises the steps as follows: A, setting test content of internal logic of a field programmable gate array of the board card; B, obtaining related data and / or signals of the internal logic of the field programmable gate array of the board card according to the test content; and C, testing the internal logic of the field programmable gate array of the board card according to the data and / or the signals. The internal logic of the field programmable gate array of the board card can be tested on line and / or remotely.

Description

technical field [0001] The invention relates to the technical field of computers, in particular to a method for testing boards and a system thereof. Background technique [0002] As the capacity and complexity of FPGA (Field-Programmable Gate Array, Field-Programmable Gate Array) become larger and larger, the code simulation speed of the logic of the Field-Programmable Gate Array board becomes slower and slower. It is almost impossible for simulation to completely cover all codes and functions. This will inevitably lead to some bugs that are not easy to find inside the FPGA. Especially when there is no problem in the laboratory test of the board, but when the board is working in the actual environment, or the working environment is particularly harsh, and the function is abnormal, the engineer has no way to go to the field environment to locate the error. [0003] see figure 1 , in the prior art, the traditional positioning method uses an oscilloscope to monitor certain o...

AI Technical Summary

Problems solved by technology

This will inevitably lead to some bugs that are not easy to find inside the FPGA.

Especially when there is no problem in the laboratory test of the board, but when the board is working in the actual environment, or the working environment is particularly harsh, and the function is abnormal, the engineer has no way to go to the field environment to locate the error

[0003] see figure 1 , in the prior art, the traditional positioning method uses an oscilloscope to monitor certain output pins of the FPGA or uses a logic analyzer built in the FPGA development tool to collect internal registers, while the oscilloscope can only monitor the output signals Monitoring, logic analyzer needs JTAG (Joint Test Action Group, joint test action group) interface for loading test, which can be used in laboratory environment, but in the actual environment, there are board space or the influence of JTAG line length and signal quality, So a logic analyzer cannot be used in all cases

[0004] On the other hand, when the user logic is abnormal and needs to be debugged, the above situation can only be tested by the online logic analyzer that comes with the compilation tool. However, when the amount of data required for testing is large, the internal resources of the FPGA cannot meet the requirements. And when the board is in the actual working environment, due to the limitation of the environment and the space of the board, the engineer has no way to debug the logic analyzer online, and it is difficult for the engineer to quickly determine the logic problem

Therefore, the existing board test technology is difficult to test the internal logic function of FPGA in the laboratory test environment and the actual working environment

[0005] In summary, the existing board test technology obviously has inconvenience and defects in actual use, so it is necessary to improve it

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