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Error correction method of cyclic hamming code based on parallel coding and decoding

An error correction method and Hamming code technology are applied in the direction of redundant code error detection and response error generation, which can solve the problems of increasing the area of ​​SRAM and register peripheral EDAC circuits, etc.

Inactive Publication Date: 2013-09-18
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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Problems solved by technology

But (22,16) Hsiao code needs 6 redundant parity bits, which increases the area of ​​SRAM and register peripheral EDAC circuit

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  • Error correction method of cyclic hamming code based on parallel coding and decoding
  • Error correction method of cyclic hamming code based on parallel coding and decoding
  • Error correction method of cyclic hamming code based on parallel coding and decoding

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Embodiment Construction

[0020] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0021] figure 1 A flow chart of an error correction method based on a parallel encoding and decoding cyclic Hamming code provided by an embodiment of the present invention, including the following steps:

[0022] Step 101. Acquire a recursive relational expression among the data in the five registers of the serial CRC encoding circuit. which is:

[0023] s 4 i + 1 = s 3 i s 3 i ...

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Abstract

The invention relates to the technical field of error correction codes, and discloses an error correction method of a cyclic hamming code based on parallel coding and decoding. The method comprises the steps that a structure of the traditional serial cyclic redundancy check (CRC) coding circuit is analyzed; a recurrence relation among data in five registers of the serial CRC coding circuit is obtained; the recurrence relation is expanded; a relational expression between a check bit and an information bit in the parallel coding is obtained; the parallel coding is performed according to the relational expression between the check bit and the information bit in the parallel coding; a relational expression between a new check bit and a new coded character code in the parallel decoding is obtained; the parallel decoding is performed; a code word is obtained; and finally, the code word obtained through the parallel decoding is subjected to error correction. The method adopts a parallel mode to perform coding and decoding on input data, so that the coding speed and the decoding speed of an input signal are increased, the error correction of the input signal is realized, and the added check bits are minimum.

Description

technical field [0001] The invention relates to the technical field of error-correcting codes, in particular to an error-correcting method of a cyclic Hamming code based on parallel coding and decoding. Background technique [0002] CRC (Cyclic Redundancy Check, Cyclic Redundancy Check Code) is an efficient error correction code. Its cyclic encoding and decoding characteristics make it widely used in improving the reliability of communication, automatic control and memory. The usual CRC encoding and decoding is implemented in a serial manner. The circuit required for encoding and decoding in this scheme is very small, but the encoding and decoding time depends on the clock cycle and the length of the code word. Therefore, the circuit speed is extremely demanding. It is not suitable for high occasions. [0003] (22,16) Hsiao code is a commonly used linear block code, an error-correcting code (SECDED) capable of correcting one error and detecting two errors. Through its corr...

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Application Information

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IPC IPC(8): G06F11/10
Inventor 刘鑫赵发展韩郑生
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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