Histogram statistic realization device and method applied to DSP (digital signal processor)

Abstract

A histogram statistic realization device applied to a DSP (digital signal processor) comprises a lookup table module, a read control module, a write control module, a lookup table correlation module and a register block. The read control module and the lockup table correlation module are on a fetching level, the lockup table module is on an executive level, the write control module is on a return level, and the lockup table module is composed of four SRAMs (static random access memories); the read control module generates an address and enabling and chip selection signals for reading the lock-up table module; the write control module is used for additive operation and generation of an address, data and enabling and chip selection signals for writing the lock-up table module; the lookup table correlation module generates correlation flags for write operation and read operation; the register block is used for registration of control signals and data and pipeline stall. The invention further provides a histogram statistic realization method applied to the DSP. The method and the device have the advantages that a user can randomly expand bits of pixel numbers according to overflow flags, various requirements are met, a pipeline structure is adopted, and execution efficiency is improved.

Description

technical field [0001] The invention relates to the field of gas image processing, in particular to a histogram statistics method used in image processing. Background technique [0002] Histogram statistics is an important part of image processing. Fast and efficient histogram statistics is the basis of image processing. At present, there are two existing methods to realize histogram statistics: one is implemented by software, and the other is It is realized by hardware. The current hardware implementation circuit generally consists of RAM, adder, address register, etc. RAM is generally 256 deep. [0003] In "TV Technology" Volume 36, Issue 7 (Total Issue 382), "FPGA-Based Real-time Histogram Statistical Design" paper, histogram statistics are realized by hardware, consisting of RAM, address generation, control and adder . [0004] The problem that exists in the prior art has two points: [0005] First, there is no overflow flag in the adder, if the bit width is not enou...

AI Technical Summary

Problems solved by technology

[0005] First, there is no overflow flag in the adder, if the bit width is not enough, it cannot be extended;

[0006] Second, there is no flow concept in the existing design, and the efficiency is low

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