43 results about "Overflow flag" patented technology

A method and apparatus for virtualizing and / or extending transactional memory is described herein. Transactions are executed using local shared transactional memory, such as a cache memory. Upon overflowing the shared transactional memory, the transactional memory is virtualized and / or extended into a higher-level memory, such as a system memory. Upon an overflow event, such as an eviction of a cache line previously accessed during a currently pending transaction, an overflow flag is set to notify processors / cores that the transactional memory is to be virtualized in a global overflow table. A base address of the global overflow table is also potentially stored to reference the base of the global overflow table in the higher-level memory.

The present invention discloses a fully digital conference audio mixing apparatus and method. Multi-channel audio data which are input is subjected to audio data preprocessing and then are sent to a summation module for summation, so as to obtain a multi-channel audio mixing digital sequence. After the multi-channel audio mixing digital sequence enters a gain adjustment module, the audio gain output is adjusted according to an adjustment factor parameter which is updated in real time. An overflow detection module detects whether overflow appears or not and feeds back an overflow flag to an adaptive adjustment factor calculation module. The adaptive adjustment factor calculation module calculates and updates adjustment factor parameters in real time according to the overflow flag value, and provides them to the gain adjustment module. Therefore, adaptive adjustment characteristics are achieved. The present invention realizes little noise, solves the problem of digital mixing overflow while retaining high sound quality, and has the benefits of high real-time capability and short delay.

The present invention prevents a data processor from undesirable operation stop due to an overflow of a plurality of register banks. A status register includes an overflow flag to indicate an overflow of the plurality of register banks. When an interrupt exception occurs in a state in which data has been saved to all banks of the register banks, and the accepted interrupt exception is permitted to use the register banks, a central processing unit saves data of a register set to a stack area and reflects an overflow state in the overflow flag. When the overflow flag indicates an overflow state, if data restoration from the register banks to the register set is directed, the central processing unit restores the data from the stack area to the register set.

The invention provides a fractional-multiple interpolation shaping filter and an implementation method thereof. The fractional-multiple interpolation shaping filter comprises a data synchronization module, a segmented filtering module, a resampling module and a numerically controlled oscillator control module. The numerically controlled oscillator control module generates a slow overflow flag according to baseband modulation rate input and sends the slow overflow flag to the data synchronization module to generate slow synchronous data output; the slow synchronous data output is processed by the segmented filtering module to generate a filter group output; the filter group output and a fast overflow flag as well as the time delay of a fractional time delay filter are processed by the resampling module to generate shaped filtered data. The fractional-multiple interpolation shaping filter is used for realizing fractional-multiple conversion between a user input rate and the rate after interpolation shaping filtering, and is adaptive to the ksps grade real-time adjustment of the user rate and capable of breaking through the traditional limitation on the user input rate; besides, the fractional-multiple interpolation shaping filter is light and ingenious in structure, simple in interface, and high in flexibility and applicability; the fractional-multiple interpolation shaping filter can be migrated to a programmable logic device or designed into a special integrated circuit, and the variable rate range of the filter can be expanded according to requirements.

An adder includes a number of computational stages each associated with one or more bit positions. Particular ones of the computational stages generate a sum output signal and a primary carry-output signal of the adder. A flag generation circuit is coupled to at least one of the stages and is operative to generate an overflow flag for the adder substantially in parallel with the generation of the sum output signal and the primary carry-output signal of the adder. Advantageously, the invention substantially reduces the computational delay associated with generation of the overflow flag, relative to that of conventional adders, without requiring an increase in transistor count or circuit area.

The invention relates to a method for judging the input overflowing amplitude of a pipelining type analog-to-digital converter, which has the advantages of shortening adjusting time and improving efficiency. A pipelining type analog-to-digital converter of 1.5 bit is adopted in a first level. The method is characterized by comprising the steps of: inputting a signal into the pipelining type analog-to-digital converter, enabling a first-level digital circuit to adopt a 3-bit digital encoding mode and enabling other digital circuits to output in a traditional digital encoding mode; adding the initial bit of the later level and the last bit of the former level to finish the output of added digits, wherein the output initial bit of the first-level digit does not participate in an addition process and is an internal overflowing judging bit; judging on negative overflowing or positive overflowing when digit output after programming settings are added, the internal overflowing judging bit, and the corresponding highest bit of the sum of the output rest levels except the first level meet corresponding conditions; and then, setting an overflowing flag signal to be 1, fully negating the data subjected to output of the added digits to acquire final digit output, i.e. to acquire accurate amplitude in a measuring range within 0.5 time.

The present invention provides a predictive M / T speed measurement method, said speed measurement method comprising the following steps: obtaining the current encoder pulse number QPOS; detecting the overflow flag COEF in the status register, and judging whether the overflow flag COEF is equal to the first preset Set a value; when the overflow flag COEF is equal to the first preset value, the capture cycle value is set to a preset maximum value and reset the overflow flag COEF; when the overflow flag COEF is not equal to the first preset value, capture timing value and capture period value; according to the capture timing value and capture period value, the first ratio is obtained; the rotation direction of the encoder is obtained, and according to the rotation direction of the encoder, the first fixed-point number PosVal and the first ratio, the first ratio is obtained An encoder pulse number; according to the first encoder pulse number, the encoder pulse number of the last cycle and the preset encoder line number, a second ratio is obtained; according to the second ratio, the preset sampling period and the preset maximum speed to get the normalized current speed value.

A highly reliable and low computational load heart rhythm recognition circuit and method applicable in a wearable device. The circuit comprises at least one software filter, one normally open software phase-locked loop, at least one backup software phase-locked loop, and at least one control logical unit K. Each backup software phase-locked loop is connected in parallel to the normally open software phase-locked loop. A signal output end of the software filter is connected respectively to the normally open software phase-locked loop and the backup software phase-locked loop. The normally open software phase-locked loop and each backup software phase-locked loop respectively comprise a heart rhythm signal output end and a frequency overflow flag output end. The heart rhythm signal output ends and the frequency overflow flag output ends respectively are connected to control logical unit K. The circuit has a lowered requirement on the signal-to-noise ratio of a signal, great robustness, and a broad recognition range. The method has an extremely low requirement on a processor, low power consumption, high reliability, and low computational load and is applicable in a wearable device.

The invention discloses a time pulse synchronization method based on an RDSS satellite navigation system. According to the method, based on a local clock, time deviation between the local clock and BDT is worked out according to time stamps and deviation adjustment information which are carried by RDSS downlink signals; the time deviation is adjusted to an output local clock overflow flag, and a pulse per second is output at the overflow moment. Because the local clock is adopted as reference in the adjustment process, time synchronization reliability is effectively improved.

A method and apparatus for virtualizing and / or extending transactional memory is described herein. Transactions are executed using local shared transactional memory, such as a cache memory. Upon overflowing the shared transactional memory, the transactional memory is virtualized and / or extended into a higher-level memory, such as a system memory. Upon an overflow event, such as an eviction of a cache line previously accessed during a currently pending transaction, an overflow flag is set to notify processors / cores that the transactional memory is to be virtualized in a global overflow table. A base address of the global overflow table is also potentially stored to reference the base of the global overflow table in the higher-level memory.

In the present invention, voice chip address line AO-A9 is connected with PO mouth P0.0-P0.7 and P1 mouth P1.0-1.1 of monolithic computer, input end P / R of voice chip record-playback mode selection control, input end of energy saving mode control, input end CE of wafer selective signal and input end OVE of overflow flag are connected with P1 mouth P1.2-1.5 of the monolithic computer separately; output end EOM of voice chip information end flag is connected with external interrupt input INT1 of the monolithic computer, output signal of voice chip is conencted with phone line via capacity coupler 1 by its SP+ end together with signal amplifying circuit and phone line input signal is connected to MIC end of ISD2590 chip via capacity coupler 2.

A counter IP core connected with a 16-bit microprocessor application system, including data input and output and command word decomposition storage control module, pulse 200 frequency divider, counting processing control module, counter overflow flag control module and input gate selection control Module; the present invention uses FPGA design counter IP core hard connection control circuit, counter IP core has 15 16-bit counters, 14 of which can form 7 32-bit counters, one command word sets the operating mode of a counter, and counts and filters the reference clock Frequency division multiple, working state control; the present invention does not occupy 16-bit microprocessor program execution time except that the 16-bit microprocessor performs function and state setting, counting parameter transmission, and counting current value operation on the counter; each 16 The bit / 32-bit counter has the function of automatically reloading counting parameters; it can meet the needs of a large number of counter counting and counting control systems.

The invention provides a method for synchronizing data transmission of printing consumable chips. The data is stored in the memory of the electronic module of the printing consumable chip. The electronic module is provided with a micro-controller which can exchange information with the outside. The return time of returning data to the outside. There is a counter in the microcontroller. The method includes determining the reference time, applying the integer multiple of the reference time setting and a remaining time accumulation result to represent the return time, and the reference time, reference time The integer multiple of the time setting and the remaining time are stored in the memory. The microcontroller judges whether the information transmitted from the outside is received. If it is to start the counter and generate the returned data, it judges the number of times the counter overflow flag is set and the integer set by the reference time. The times are equal, so the return data is sent when the counter counts to the end of the remaining time. The present invention can use the counter with fewer digits to realize the timing of the return time and reduce the production cost of the electronic module.