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Global overflow method for virtualized transactional memory

A technology of transaction memory and memory, which is applied in memory systems, instruments, memory address/allocation/relocation, etc., and can solve problems such as time waste

Inactive Publication Date: 2008-01-02
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in previous hardware TM systems, if a transaction became too large for memory, i.e. overflowed, the transaction was usually restarted
Here the time spent executing the transaction all the way to overflow may be wasted

Method used

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  • Global overflow method for virtualized transactional memory
  • Global overflow method for virtualized transactional memory
  • Global overflow method for virtualized transactional memory

Examples

Experimental program
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Embodiment Construction

[0024] In the following description, numerous specific details are set forth, such as examples of specific hardware support for transactional execution, specific types of locals / memory in processors, and specific types of memory accesses and locations, etc., in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that these specific details are not required to practice the invention. In other cases, details such as encoding of transactions in software, partitioning of transactions, specific multi-core and multi-threaded processor architectures, interrupt generation / handling, cache organization, and specific operational details of microprocessors are not described in detail well-known components or methods in order not to unnecessarily obscure the understanding of the present invention.

[0025] Methods and apparatus described herein are used to extend and / or virtualize transactional memory (TM) to support o...

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PUM

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Abstract

A method and apparatus for virtualizing and / or extending transactional memory is described herein. Transactions are executed using local shared transactional memory, such as a cache memory. Upon overflowing the shared transactional memory, the transactional memory is virtualized and / or extended into a higher-level memory, such as a system memory. Upon an overflow event, such as an eviction of a cache line previously accessed during a currently pending transaction, an overflow flag is set to notify processors / cores that the transactional memory is to be virtualized in a global overflow table. A base address of the global overflow table is also potentially stored to reference the base of the global overflow table in the higher-level memory.

Description

technical field [0001] The present invention relates to the field of processor execution, and in particular, to executing groups of operations. Background technique [0002] Advances in semiconductor processing and logic design have allowed for an increase in the amount of logic that can exist on an integrated circuit device. Consequently, computer system configurations have evolved from single or multiple integrated circuits in the system to multiple cores and multiple logical processors present on each integrated circuit. A processor or integrated circuit typically includes a single processor die, where a processor die may include any number of cores or logical processors. [0003] As an example, a single integrated circuit may have one or more cores. The term "core" generally refers to the ability of logic on an integrated circuit to maintain independent architectural states, where each independent architectural state is associated with at least a portion of dedicated e...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/08
CPCG06F12/0815G06F12/02G06F12/08G06F9/22
Inventor J·巴恩斯R·拉瓦
Owner INTEL CORP
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