Counter IP core connected with 16-bit microprocessor application system, and counter counting control realization method thereof

An application system and microprocessor technology, applied in the direction of machine execution devices, etc., can solve the problems of heavy maintenance workload and large circuit scale

Inactive Publication Date: 2015-12-02
GUANGXI UNIVERSITY OF TECHNOLOGY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The third method is to use non-programmable hardware counting, and each counter is realized by an independent hardware circuit; in this way to realize the counting function, the more counters are required, the larger the circuit scale and the maintenance workload is.

Method used

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  • Counter IP core connected with 16-bit microprocessor application system, and counter counting control realization method thereof
  • Counter IP core connected with 16-bit microprocessor application system, and counter counting control realization method thereof
  • Counter IP core connected with 16-bit microprocessor application system, and counter counting control realization method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0245] A kind of counter IP core connected with 16-bit microprocessor application system

[0246] Such as figure 1 As shown, the counter IP core includes data input and output and command word decomposition storage control module II, pulse 200 frequency divider III, counting processing control module IV, counter overflow flag control module V, input gate selection control module VI;

[0247] The data input and output and command word decomposition storage control module II are connected with the 16-bit microprocessor application system I, the counting processing control module IV, the counter overflow flag control module V and the input gate selection control module VI;

[0248] The pulse 200 frequency divider III is also connected with the 16-bit microprocessor application system I and the counting processing control module IV;

[0249] The counting processing control module IV is also connected with the 16-bit microprocessor application system I, the counter overflow flag c...

Embodiment 2

[0384] A counter IP core connected to a 16-bit microprocessor application system, each counter of the counter IP core converts the frequency division multiples of the sixteen kinds of filter reference clock pulses that can be selected and set in Embodiment 1 into each counter that can be selected The frequency division multiples of eight kinds of filtering reference clock pulses are set, and its basic structure is the same as that of Embodiment 1, the difference is that the frequency division multiples after its transformation and the counter counting control operation program flow are different;

[0385] The frequency division multiple setting after its transformation is set to refer to attached table three: "the counter command word of the counter IP core of embodiment two and the counter IP core that 16-bit microprocessor application system is connected"; Fig. 6_1~6_3 counter counting control operating program flow of embodiment one Fig. 7_1~7_3 is transformed into the flow ...

Embodiment 3

[0406] A counter IP core connected with a 16-bit microprocessor application system, figure 1 The pulse 200 frequency divider III determines the filter reference clock of the counter IP core, transforms the pulse 200 frequency divider III into a 400 frequency divider III, and adapts to the case where the clock frequency of the 16-bit microprocessor is greater than 50MHz.

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Abstract

A counter IP core connected with a 16-bit microprocessor application system comprises a data input/output and command word decomposition storage control module, a pulse 200 frequency divider, a counting processing control module, a counter overflow sign control module and an input gated selection control module; the FPGA design counter IP core is in hard connection with a control circuit; the counter IP core comprises 15 16-bit counters, wherein 14 counters can form 7 32-bit counters; one command word sets the work mode of the counter, sets counting filtering reference clock frequency division times, and controls the work state; the counter IP core only uses the 16-bit microprocessor to set functions and states, counting parameter transmission and read counting present value operation of the counters, so program execution time of the 16-bit microprocessor is not used by other programs; each 16/32 bit counter has a counting parameter automatic afresh loading function, thus satisfying counting and counting control system demands of many counters.

Description

technical field [0001] The present invention relates to a counter IP core connected with a 16-bit microprocessor application system and a method for realizing counter counting control thereof, in particular to a feature based on FPGA parallel processing, which can be combined with a 16-bit microcomputer by using FPGA to design a hard-connected circuit. A counter IP core connected to a microprocessor application system and a method for realizing counter counting control. Background technique [0002] In large-scale counting control or other 16-bit microprocessor application systems that require the application of many counters, a large number of counters will be used. There are three ways to implement the expansion of the number of counters: the first way is to use a counter in the microprocessor The count value is used as the base count value, and the counting interrupt method is used to program, and the multiple variable of the base count value is set. The count value multi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/30
Inventor 蔡启仲潘绍明柯宝中李克俭
Owner GUANGXI UNIVERSITY OF TECHNOLOGY
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