Radix-minus-one complement adder

Abstract

The invention discloses a radix-minus-one complement adder. The radix-minus-one complement adder comprises a sign processing unit, a negation unit, a parallel prefix adder body, an overflow judging unit and an operation result selecting and processing unit, wherein the sign processing unit is used for receiving a first operand and a second operand and judging the sign bit of the first operand and the sign bit of the second operand to obtain a first judgment result; the negation unit is used for carrying out negation on the first operand and the second operand according to the first judgment result; the parallel prefix adder body is used for carrying out operation on the first operand and the second operand after negation to obtain sum and sum+1; the overflow judging unit is used for carrying out overflow judgment on the sign bit of sum, the sign bit of sum+1, the sign bit of the first operand and the sign bit of the second operand to obtain a second judgment result; the operation result selecting and processing unit is used for selecting sum or sum+1 according to the second judgment result to be subjected to negation so as to obtain a final operation result. The structural area of the adix-minus-one complement adder is reduced, the delay time of critical paths is shortened, and operation efficiency is improved.

Description

technical field [0001] The invention relates to the technical field of digital signal processing, in particular to an inverse code adder. Background technique [0002] The adder is the basic and core of the processor for data processing, which directly affects the performance of the processor. The pursuit of high-efficiency and low-power adders has always been a research goal. [0003] When performing signed calculations, the operands use the sign-magnitude representation. When the adder handles the subtraction of signed numbers, it first converts the operands into complement or complement form, and then converts the calculation result into the original code after the operation is completed. However, when the inverse code operation is used, if a cyclic carry is generated during the calculation process, the addition operation needs to be repeated; while the complement code operation needs to be converted back and forth between the original code and the complement code. The...

AI Technical Summary

Problems solved by technology

Therefore, the above two commonly used adder structures have the disadvantages of long delay time and large area.

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