Data processing method and device

A data processing and processor technology, applied in the field of coding, can solve the problem of high logic resources, achieve the effect of reducing the occupation of logic resources, reducing the data bit width, and increasing the working frequency
CN106877882BActive Publication Date: 2020-03-31SHENZHEN YILIAN INFORMATION SYST CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
SHENZHEN YILIAN INFORMATION SYST CO LTD
Publication Date
2020-03-31

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Abstract

The invention relates to a data processing method and device. The method comprises the steps that data to be encoded are acquired; a second generation matrix is selected to encode the message segment of the data to be encoded, wherein the message segment is formed by segmenting the data to be encoded according to the dimensionality of a first generation matrix, and the second generation matrix is formed by replacing each cyclic matrix in the first generation matrix with a quasi-cyclic matrix; the quasi-cyclic matrix is a matrix comprising a number of cyclic sub-matrices; and the product of the number of the cyclic sub-matrices of each row of the quasi-cyclic matrix and the dimension of the cyclic sub-matrices is equal to the dimension of the cyclic matrix. According to the invention, a code generation matrix is transformed; without changing the quasi-cyclic characteristic of the generation matrix, the data bit width of encoding operation is reduced; the logical resource occupancy of the operation is reduced; and the operating frequency of encoding calculation is improved.
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Description

technical field

[0001] The present disclosure relates to the technical field of coding, and in particular, to a data processing method and device. Background technique

[0002] Quasi-cyclic low-density parity-check codes (Quasi-cyclic Low-density Parity-check, QC-LDPC codes for short) have been widely verified in the industry to have the same excellent bit error performance as randomly constructed LDPC codes. One of the commonly used coding schemes for QC-LDPC codes is to use a shift register adder accumulator (SRAA structure for short) to achieve linear coding complexity by virtue of the quasi-cyclic property. In this encoding scheme, the data bit width of the encoding operation is the cycle length of the QC-LDPC code. The logic resource occupation of the encoder is directly related to the cycle length, and register resources at least twice the cycle length are required. Therefore, for the QC-LDPC code with a large cycle length, the logic resources required to implement th...

Claims

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