Method for increasing coding rate of TLC flash

A coding rate and flash memory technology, which is used in the generation of response errors, redundant codes for error detection, instruments, etc., can solve the problems of low coding rate and small length of user data, and achieve the effect of improving the coding rate

Inactive Publication Date: 2018-07-06
SHENZHEN YILIAN INFORMATION SYST CO LTD
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Problems solved by technology

The fixed LDPC algorithm is used to ensure the overall security, so the length of the verification data is selected to be the largest. The problem is that the length of the user data is small and the overall encoding rate is low.

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  • Method for increasing coding rate of TLC flash
  • Method for increasing coding rate of TLC flash
  • Method for increasing coding rate of TLC flash

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Embodiment Construction

[0017] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0018] In the prior art, the TLC NAND adopts the LDPC error correction algorithm throughout the life cycle, and the encoding rate=user data size / (user data size+LDPC check data size). figure 2 It is the relationship between BER and PE Cycle of various types of flash memory. The BER of TLC NAND increases monotonously with the PE Cycle. When the PE Cycle is small, the BER is also relatively small. At this time, the BCH error correction algorithm is completely suffici...

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Abstract

The invention discloses a method for increasing a coding rate of a TLC flash. The method is characterized in that when an erasure frequency of a Block is smaller than a preset erasure inflection pointfrequency PE_tr, BCH is selected as a BER error correction algorithm of the Block; and when the erasure frequency of the Block is not smaller than the preset erasure inflection point frequency PE_tr,LDPC is selected as the BER error correction algorithm of the Block. By dynamically adjusting an error correction algorithm strategy in a life cycle of TLC NAND, namely, dynamically adjusting check data size, the coding rate of the TLC flash is expectedly improved on the whole.

Description

technical field [0001] The invention relates to solid-state hard disk control technology, in particular to a method for improving the coding rate of TLC flash memory. Background technique [0002] The data on the flash memory (NAND) may be wrong, that is, the read data is inconsistent with the written data, so we need to generate some check data in addition to the user data, and use it to correct the error when the data is wrong. Coding rate of a page=user data size / (user data size+check data size). At present, there are two mainstream error correction algorithms, BCH (Bose, Ray-Chaudhuri and Hocquenghem) algorithm and LDPC (Low Density Parity Check Code) algorithm. BCH has weak error correction ability, but requires less verification data and faster error correction. Fast, suitable for SLC (Single-Level Cell) and MLC (Multi-Level Cell) NAND; LDPC has strong error correction capability, but requires a lot of verification data and slow error correction speed, and is suitable...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/10
CPCG06F11/1012G06F11/1048G06F11/1068
Inventor 许毅姚兰郑春阳
Owner SHENZHEN YILIAN INFORMATION SYST CO LTD
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