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Impedance configuration method of memory interface and computer-readable storage medium

A technology of memory interface and configuration method, which is applied in the field of computer-readable storage medium and impedance configuration of memory interface, and can solve problems such as pin line reflection and signal transmission problems.

Active Publication Date: 2022-05-31
SILICON MOTION INC (CN)
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Problems solved by technology

[0002] After the speed of the DRAM (Dynamic Random Access Memory DRAM) bus reaches a high transfer rate, such as 500Mb / s or higher, system-level signaling problems may occur, for example, from connected peer devices (such as controllers, DRAM modules, etc.)

Method used

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  • Impedance configuration method of memory interface and computer-readable storage medium

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Embodiment Construction

[0045] The embodiments of the present invention will be described below with reference to the related drawings. In the figures, the same reference numbers refer to the same or similar components or method flows.

[0046] It must be understood that words such as "comprising" and "including" used in this specification are used to indicate the existence of specific technical features, values, method steps, job processes, components and / or components, but do not exclude the possibility of Plus more technical features, values, method steps, job processes, components, components, or any combination of the above.

[0047] The use of words such as "first", "second" and "third" in the present invention is used to modify the components in the claims, and is not used to indicate that there is a priority order, a precedence relationship, or a component precedence Another component, or the chronological order in which method steps are executed, is only used to distinguish components with ...

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Abstract

The present invention proposes an impedance configuration method of a memory interface, which is executed by a processing unit, including: setting the first resistance value of the on-chip termination resistor associated with the first receiver as a first default resistance value; setting the resistance value associated with the second receiver The second resistance value of the drive variable resistor of the transmitter is set to the second default resistance value; the test is performed for a plurality of test combinations, where each combination includes a third resistance value of the drive variable resistor associated with the first transmitter and the fourth resistance value of the on-chip termination resistor associated with the second receiver; and storing the test results of each test combination to a specific location of the SRAM, so that the calibration host can obtain each test result from the SRAM. The test results of each test combination, and determine the impedance setting of the memory interface according to the test results.

Description

technical field [0001] The present invention relates to a communication interface, in particular to an impedance configuration method of a memory interface and a computer-readable storage medium. Background technique [0002] After the speed of the Dynamic Random Access Memory (DRAM) bus reaches a high transfer rate, such as 500Mb / s or higher, system-level signaling problems may occur, for example, from connected peer devices (such as controllers, DRAM modules, etc.) pin lines produce reflections. The above-mentioned signal transmission problem can be solved by adjusting the driver (Driver) and the on-die termination resistor (On-Die Termination ODT). Therefore, the present invention provides a configuration method of a memory interface and a computer-readable storage medium, which are used for calibrating a driver in a memory interface and an in-chip termination resistor. SUMMARY OF THE INVENTION [0003] In view of this, how to alleviate or eliminate the above-mentione...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C29/50G11C29/56
CPCG06F11/2273G06F11/2221
Inventor 宋威良张启彬
Owner SILICON MOTION INC (CN)
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