Task acceleration optimization method and device based on priority partitioning

An optimization method and priority technology, applied in the field of data processing, can solve problems such as unstable execution time, achieve the effect of stable interrupt running time, and meet the requirements of rapidity and stability

Active Publication Date: 2020-12-25
NARI TECH CO LTD +1
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  • Application Information

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Problems solved by technology

[0005] The purpose of the present invention is to solve the problem of unstable execution time caused by high-priority task Cache and DDR-ram switching, and to provide a method and device for accelerating task execution optimization based on priority partitioning, which partitions code instructions according to priority, and compiles The link automatically links codes with different priorities, and finally realizes that high-priority codes are locked in the internal high-speed Cache memory, and realizes hard real-time execution of high-priority tasks

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  • Task acceleration optimization method and device based on priority partitioning
  • Task acceleration optimization method and device based on priority partitioning
  • Task acceleration optimization method and device based on priority partitioning

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Embodiment Construction

[0059] The present invention will be further described below. The following examples are only used to illustrate the technical solution of the present invention more clearly, but not to limit the protection scope of the present invention.

[0060] The present invention provides a task acceleration execution optimization method based on priority partitioning, which is used to solve the problem of excessive running time jitter caused by the uncertainty of Cache hits in the operation of general CPU high-priority tasks. For the principle, see image 3 , first divide the CPU Cache into two areas, namely the CPU usage area and the reserved area. The sizes of the two areas are estimated and preset according to the size of the high-priority task code occupation space, and the reserved area is the high-priority task locked area. , the CPU usage area is scheduled and used by the CPU itself. High-priority interrupt service routines are all locked in the Cache before starting, so that wh...

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Abstract

The invention discloses a task accelerated execution optimization method and device based on priority partitions, and the method comprises the steps: pre-defining task priorities, and configuring memory partitions and mark characters for all priority tasks; before an application service program is compiled, predefined mark characters are automatically placed in a task function corresponding to a priority task and a data area of the task function through a tool, and the tasks with the same priority are divided into the same continuous memory partition when the program is linked. In the programguiding process, the code with the highest priority is locked in the instruction Cache, so that the code instruction with the highest priority can run with higher efficiency and more stable executiontime, and the problems of unstable execution time and low execution efficiency caused by high-priority interruption when a universal CPU is adopted to replace a special DSP are solved.

Description

technical field [0001] The invention belongs to the technical field of data processing, and in particular relates to a task acceleration and optimization method and device based on priority partitioning. Background technique [0002] With the improvement of integration and performance of general-purpose CPU, the development of special-purpose digital signal processor DSP has been severely restricted, and it has gradually become a trend to replace special-purpose DSP with general-purpose CPU. At present, major DSP manufacturers (such as TI and ADI) have stopped investing in new DSP development roadmaps, and have also begun to increase investment in general-purpose CPUs. As a complete machine manufacturer, it is also necessary to keep up with the trend of technological development, otherwise the complete machine integration will not be able to keep up with the market competition environment. However, general-purpose CPU chips generally do not have the concept of DSP's on-chip...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/50G06F8/72G06F9/54
CPCG06F9/5027G06F9/5038G06F9/546G06F8/72G06F9/5016G06F2209/5021G06F2209/548
Inventor 李友军周华良郑玉平高诗航郑奕刘拯戴欣欣罗华煜张吉
Owner NARI TECH CO LTD
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