Mixed base DFT processing method, apparatus and device, and storage medium

A processing method and hybrid-based technology, which are applied in machine execution devices, complex mathematical operations, concurrent instruction execution, etc., can solve problems such as multi-time, waste, and time-consuming, and achieve the effect of improving computing speed.

Pending Publication Date: 2021-04-16
上海金卓科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This method needs to put all the DFT points of the design into the hardware, so that the ASIC chip has a certain degree of versatility, but this leads to higher costs
[0003] In addition, for the specific number of DFT points required by the proprietary network, if ASIC hardware implementation is used, it needs to be redesigned and taped out, which not only increases the cost but also takes a long time
When using software to implement, if the non-vector method is used, it will take a long time to complete a DFT calculation. Even if the software vector method is used to complete, if the vector resources cannot be fully utilized, it will still take more time.

Method used

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  • Mixed base DFT processing method, apparatus and device, and storage medium
  • Mixed base DFT processing method, apparatus and device, and storage medium
  • Mixed base DFT processing method, apparatus and device, and storage medium

Examples

Experimental program
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Effect test

Embodiment 1

[0045] figure 1 It is a flow chart of a mixed-radix DFT processing method in Embodiment 1 of the present invention. This embodiment is applicable to the situation where the rapid processing of mixed-radix DFT of any combination of points is realized by software, and the method can be processed by mixed-radix DFT The device can be implemented by hardware and / or software, and can generally be integrated in an electronic device that provides DFT calculation services. Such as figure 1 As shown, the method includes:

[0046] Step 110: Divide the mixed basis corresponding to the original input sequence to be calculated into multiple calculation levels, and determine the target calculation level for sequence rearrangement according to the number of DFT points of the original input sequence.

[0047] In this embodiment, the original input sequence to be calculated is sequential DFT input data, that is, the data to be processed by DFT, and the mixed basis may be a multiplier factor o...

Embodiment 2

[0061] Figure 2a It is a flow chart of a mixed-radix DFT processing method in Embodiment 2 of the present invention. This embodiment is further refined on the basis of the above-mentioned embodiment, and provides a method for determining the sequence rearrangement that needs to be performed according to the number of DFT points of the original input sequence. The specific implementation of the target computing level, the specific implementation of reordering multiple levels of input sequences input to the target computing level into one target sequence according to the set standard, etc. Combine below Figure 2a A mixed-radix DFT processing method provided in Embodiment 2 of the present application is described, including the following steps:

[0062] Step 210, obtain the original input sequence and the mixed basis, and divide the mixed basis into multiple calculation levels.

[0063] In this embodiment, the original input sequence is sequential DFT input data. Before perfo...

Embodiment 3

[0095] image 3 It is a schematic structural diagram of a mixed-radix DFT processing device in Embodiment 3 of the present invention. This embodiment is applicable to the situation that the rapid processing of mixed-radix DFT of any combination of points is realized by software. The device can be composed of hardware and / or It can be implemented by software, and can generally be integrated in electronic devices that provide DFT calculation services. Such as image 3 As shown, the device includes:

[0096] The preprocessing module 310 is used to divide the mixed basis corresponding to the original input sequence to be calculated into a plurality of calculation levels, and determine the target calculation level for sequence rearrangement according to the DFT points of the original input sequence;

[0097] The reordering module 320 is used to reorder the input sequences of multiple levels input to the target calculation level according to the set standard during the execution o...

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Abstract

The embodiment of the invention discloses a mixed base DFT processing method, device and equipment and a storage medium. The method comprises the following steps: dividing a mixed base corresponding to a to-be-calculated original input sequence into a plurality of calculation levels, and determining a target calculation level needing sequence rearrangement according to the number of DFT points of the original input sequence; in the process of executing the DFT processing operation on the original input sequence by calculation hierarchy, if the original input sequence is executed to a target calculation hierarchy, reordering a plurality of hierarchy input sequences input to the target calculation hierarchy into a target sequence according to a set standard; and performing DFT processing corresponding to the target calculation hierarchy on the target sequence. According to the technical scheme of the embodiment of the invention, the calculation speed of the DFT is improved by fully utilizing the vector resources, and the mixed base DFT of any point number combination can be realized.

Description

technical field [0001] Embodiments of the present invention relate to the technical field of digital signal processing and communication, and in particular, to a mixed-radix DFT processing method, device, device, and storage medium. Background technique [0002] In the prior art, when realizing the mixed base discrete Fourier transform (Discrete Fourier Transform, DFT), in order to make the calculation speed of the DFT reach the fastest, the hardware is basically implemented in the form of an application specific integrated circuit (ASIC). accomplish. This method needs to incorporate all the designed DFT points into the hardware, so that the ASIC chip has certain versatility, but this leads to higher costs. [0003] In addition, for the specific DFT points required by the proprietary network, if ASIC hardware is used to implement it, it needs to be redesigned and taped out, which not only increases the cost but also takes a long time. When using software to implement, if t...

Claims

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Application Information

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IPC IPC(8): G06F17/14G06F9/38
Inventor 张家辉
Owner 上海金卓科技有限公司
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