Memory cell and manufacturing method thereof

Abstract

The invention provides a memory cell and a manufacturing method thereof, and the memory cell comprises a vertical transistor which is partially arranged in a substrate, wherein the vertical transistor is provided with a source electrode, a grid electrode and a drain electrode from bottom to top, the grid electrode is connected with a word line, and the source electrode is connected with a bit line; a storage contact structure which comprises an embedded part located in the first groove, wherein the side face of the first groove is wrapped by an isolation structure, and the lower surface of the embedded part is connected with the drain electrode of the vertical transistor; a protruding part which is located on the embedded part and connected with the upper surface of the embedded part, wherein the protruding part is of a columnar structure; a storage capacitor which is provided with a lower pole plate, a dielectric layer and an upper pole plate, wherein the lower pole plate is attached to the side surface of the protruding part, the dielectric layer is attached to the lower pole plate and the upper surface of the protruding part, and the upper pole plate is attached to the dielectric layer. According to the embodiment of the invention, the structural strength and the arrangement density of the storage unit can be improved.

Description

technical field [0001] The present disclosure relates to the technical field of integrated circuit manufacturing, and in particular, to a storage unit and a manufacturing method thereof. Background technique [0002] With the development of integrated circuit manufacturing technology, the device size is getting smaller and smaller, and the arrangement density is getting higher and higher, which poses a huge challenge to the manufacturing process. [0003] In the DRAM manufacturing process, vertical memory cells (composed of vertical transistors and vertical capacitors) have become a new technology to increase the number of memory cells per unit area. In the vertical memory cell, the source, gate, and drain of the transistor are arranged in sequence from bottom to top, the storage capacitor is located above the drain of the transistor, and the lower plate of the capacitor is connected to the transistor through the storage contact structure (Stock NodeContact, SNC). drain con...

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present disclosure is to provide a memory cell and its manufacturing method, which are used to overcome at least to some extent the problem of insufficient structural stability of vertical capacitors in the case of high-density arrangement due to the limitations and defects of related technologies

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