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Symmetric decoding device of polarization code

A decoding device and polar code technology, applied in the field of polar code symmetric decoding devices, can solve problems such as decoding failure, achieve the effect of improving performance and reducing misjudgment of decoding paths

Pending Publication Date: 2021-07-27
BEIJING RINFON TECH CO LTD
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Problems solved by technology

[0031] However, the existing SC decoding algorithm makes a hard decision on the nodes of each layer during decoding and then continues to expand downwards. In the code tree, it is shown that since the SC decoding algorithm only selects the path with the largest metric value for expansion, then Once it deviates from the correct path during the expansion process, it will cause decoding failure

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  • Symmetric decoding device of polarization code
  • Symmetric decoding device of polarization code
  • Symmetric decoding device of polarization code

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Embodiment Construction

[0065] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0066] see Figure 1-6 The present invention provides a technical solution: a symmetrical decoding device of a polar code, comprising a modulation system of a CRC-SCL decoding algorithm and a CRC-SCL decoding algorithm, the CRC-SCL decoding algorithm comprising the following steps:

[0067] Step 1: Start the symmetrical decoding device, set the input signal according to the given value, and then input the signal to be decoded;

[0068] Step 2, according to th...

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Abstract

The invention discloses a symmetric decoding device of a polarization code, which comprises a modulation system of a CRC-SCL decoding algorithm and the CRC-SCL decoding algorithm, and the CRC-SCL decoding algorithm comprises the following steps: step 1, starting the symmetric decoding device, setting an input signal according to a given numerical value, and then inputting a signal needing to be decoded; step 2, approximately calculating transition probability recursion of L paths by using a calculation method of transition probability in a logarithm domain according to the signal input in the step 1; and step 3, recursively transmitting the calculated transition probabilities to a transition probability memory according to the transition probabilities of the L paths calculated in the step 2. According to the invention, the L candidate paths of the SCL algorithm are verified by using CRC verification, and the most reliable path satisfying the CRC verification is used as an output decoding path. The CRC-SCL decoding algorithm effectively reduces the misjudgment of a decoding path, the performance of the decoding algorithm is greatly improved, and the algorithm is convenient to realize by an FPGA.

Description

technical field [0001] The invention relates to the technical field of wireless communication, in particular to a polar code symmetric decoding device. Background technique [0002] The Polar code is a linear block code. Through encoding, the codeword will be polarized, that is, the channel capacity of some channels (bits of the codeword) approaches 0, and some approaches 1. When encoding, the bits to be encoded are placed on the bits with high channel capacity, and the redundant bits are placed on the bits with low channel capacity. Generally, the redundant bits are set to 0, which is convenient for decoding. [0003] The code length of the Polar code is , , which is a positive integer. For the encoding of the information bit length, it is first necessary to know the order of the channel capacity of each channel. Put the information bits in the channel position with the largest channel capacity, and set the remaining positions to 0, which are called frozen bits. The sequen...

Claims

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Application Information

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IPC IPC(8): H03M13/13
CPCH03M13/13
Inventor 熊军郭晓峰陈玉凤胡宁
Owner BEIJING RINFON TECH CO LTD
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