Symmetric decoding device of polarization code

Abstract

The invention discloses a symmetric decoding device of a polarization code, which comprises a modulation system of a CRC-SCL decoding algorithm and the CRC-SCL decoding algorithm, and the CRC-SCL decoding algorithm comprises the following steps: step 1, starting the symmetric decoding device, setting an input signal according to a given numerical value, and then inputting a signal needing to be decoded; step 2, approximately calculating transition probability recursion of L paths by using a calculation method of transition probability in a logarithm domain according to the signal input in the step 1; and step 3, recursively transmitting the calculated transition probabilities to a transition probability memory according to the transition probabilities of the L paths calculated in the step 2. According to the invention, the L candidate paths of the SCL algorithm are verified by using CRC verification, and the most reliable path satisfying the CRC verification is used as an output decoding path. The CRC-SCL decoding algorithm effectively reduces the misjudgment of a decoding path, the performance of the decoding algorithm is greatly improved, and the algorithm is convenient to realize by an FPGA.

Description

technical field

[0001] The invention relates to the technical field of wireless communication, in particular to a polar code symmetric decoding device. Background technique

[0002] The Polar code is a linear block code. Through encoding, the codeword will be polarized, that is, the channel capacity of some channels (bits of the codeword) approaches 0, and some approaches 1. When encoding, the bits to be encoded are placed on the bits with high channel capacity, and the redundant bits are placed on the bits with low channel capacity. Generally, the redundant bits are set to 0, which is convenient for decoding.

[0003] The code length of the Polar code is , , which is a positive integer. For the encoding of the information bit length, it is first necessary to know the order of the channel capacity of each channel. Put the information bits in the channel position with the largest channel capacity, and set the remaining positions to 0, which are called frozen bits. The sequen...

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