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Semiconductor integrated circuit

A technology of integrated circuits and semiconductors, applied in the manufacture of circuits, logic circuits, semiconductors/solid-state devices, etc.

Inactive Publication Date: 2003-02-19
SOCIONEXT INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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  • Semiconductor integrated circuit
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Embodiment 1

[0111] Figure 9 and Figure 10 Shows Example 1 of the present invention. Figure 9 (a) and (c) are configuration examples for an inverter circuit. The figure (a) is an inverter circuit in which PMOS 100 and NMOS 101 are connected in series, and the connection point of PMOS 100 and NMOS 101 is output terminal 102 .

[0112] In the inverter circuit, the source terminal of the PMOS 100 (first MOS transistor) 100 is connected to the terminal (power supply terminal) 18 of the power generator (conductance adjustment device and current adjustment device) 17, and the well terminal as the control terminal Connect to Terminal 19. In the operating state of the inverter circuit, both terminals 18, 19 are set to the first supply potential. In the non-operating state, the power supply potential of the terminal 18 is lowered to the second power supply potential Vdd2 (Vdd2<<Vdd1). At this time, if the input signal of the inverter circuit is the second power supply potential Vdd2 (H leve...

Embodiment 2

[0134] Next, Embodiment 2 of the present invention will be described. In this embodiment, the present invention is applied to SRAM. Although it is considered more difficult to apply the present invention to an SRAM than an inverter circuit, it is actually the same as an inverter circuit according to the characteristics of FIG. 7 .

[0135] Figure 11 is a structural diagram of the most widely used SRAM at present. The inverter circuit 17a (first signal processing circuit) is composed of a PMOS (first PMOS transistor) 100a and an NMOS (first NMOS transistor) 101a connected in series, and the connection point between the drain terminals thereof is an output terminal (the first output terminal). terminal) 102a, and the connection point between the gate terminals is an input terminal (first input terminal) 103a. In addition, the inverter circuit 18a (second signal processing circuit) is also composed of a PMOS (second PMOS transistor) 100b and an NMOS (second NMOS transistor) 101...

Embodiment 3

[0147] Next, Embodiment 3 of the present invention will be described. This embodiment is to apply the present invention to a NAND circuit. like Figure 16 As shown, the structure of the 2-input NAND circuit is different from that of the inverter circuit in that the NMOSs 25 and 26 are connected in series or the PMOSs 27 and 28 are connected in parallel.

[0148] Logic circuits such as NAND circuits and NOR circuits including the inverter circuits discussed above are static circuits. In the case of a static logic circuit, the point that the output is determined by switching the PMOS and NMOS on and off is the same. For example, when the input terminals 29 and 30 are set at H level and H level, the output terminal 31 becomes L level. NMOS said Figure 5 The characteristics of Non in (b), but by making the characteristics of Non correspond to the case of replacing the series connection of NMOS25 and NMOS26 with one NMOS, and making the Poff characteristics of PMOS correspond ...

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Abstract

The present invention relates to a semiconductor integrated circuit. In an operating state of an inverter circuit, terminals 18, 19 are set at a power source potential Vdd1. In the non-operating state, a power source potential of the terminal 18 is lowered to be a second power source potential Vdd2 (Vdd2< H03K 19 / 0948 1 33 29 2002 / 7 / 12 1398046 2003 / 2 / 19 1232040 2005 / 12 / 14 2005 / 12 / 14 2005 / 12 / 14 Matsushita Electric Industrial Co., Ltd. Japan Kusumoto Keiichi Kumamaru Tomoyuki Anto Takashi wang huimin 11021 The Patent Agency of the Chinese Academy of Sciences Inside the Chinese Academy of Sciences, No.52 Sanlihe Road, Fuwai, Beijing 100864 Japan 2001 / 7 / 16 2001-215352

Description

technical field [0001] The present invention relates to a semiconductor integrated circuit. Background technique [0002] In the past, in order to reduce the current in the non-operating state of the semiconductor integrated circuit, proposed figure 1 The semiconductor integrated circuit shown. Next, this semiconductor integrated circuit will be described. [0003] In the same figure, a PMOS transistor 4 (hereinafter abbreviated as PMOS) is connected between the power supply terminal 2 of the inverter circuit 1 and the power supply potential 7, and a PMOS transistor 4 is connected between the ground terminal 3 of the inverter circuit 1 and the ground potential 8. NMOS transistor 5 (hereinafter, simply referred to as NMOS). In the manufacturing stage, the threshold values ​​(absolute values) of these transistors are set larger than those of the transistors constituting the inverter circuit 1 . Therefore, when the inverter circuit 1 is in the non-operating state, as shown ...

Claims

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Application Information

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IPC IPC(8): H01L21/8238G05F1/56H01L21/8234H01L27/088H01L27/092H03K19/00H03K19/0948
CPCG05F1/56H03K19/0016
Inventor 楠本馨一熊丸知之安藤贵史后藤哲治
Owner SOCIONEXT INC
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