Communicating network exchanging system and controlling method based on parallel buffer structure

Abstract

The invention raises the high efficiency cell dispatching algorithm based on paralleled buffer exchange structure and uses paralleled buffer structure to eliminate the blockage of traffic. The invention consists of cell input, paralleling buffer, interbedded section switch system, cell output and data processor.

Description

technical field [0001] The invention relates to a communication network switching system, in particular to a communication network switching with a parallel cache structure and its control, and belongs to the technical field of communication networks. Background technique [0002] With the rapid development of optical fiber communication technology, especially the continuous maturity of high-density wavelength division multiplexing technology, the bandwidth of the communication network has been rapidly increased, making the switching system of the communication network a bottleneck for the performance improvement of the high-speed communication network. The switching efficiency is of great significance to improve the communication network performance. International-Telecommunication Union Telecommunication Standardization Sector- ITU-T) stipulates that Asynchronous Transfer Mode (ATM) is used as the core and foundation of Broadband Integrated Services Digital Network (B-ISD...

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Problems solved by technology

However, this cache structure lacks an efficient scheduling algorithm, so the throughput of the switching system is low

For example, the widely used parallel iterative matching (Parallel Iterative Matching-PIM) algorithm, after four iterations, the throughput rate can only reach 0.97, and the hardware implementation is complex. For a 16×16 switching structure, nearly 64,000 complex gate devices are required , the difficulty in hardware implementation limits its application in high-speed switching systems

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