Communicating network exchanging system and controlling method based on parallel buffer structure

A switching system and communication network technology, applied in the field of communication network switching and its control, and communication network switching system, can solve the problems of limited application, complex hardware implementation, lack of efficient scheduling algorithm in cache structure, etc., to meet real-time performance and speed fast effect

Inactive Publication Date: 2005-07-27
NANKAI UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, this cache structure lacks an efficient scheduling algorithm, so the throughput of the switching system is low
For example, the widely used parallel iterative matching (Parallel Iterative Matching-PIM) algorithm, after four iterations, the thr...

Method used

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  • Communicating network exchanging system and controlling method based on parallel buffer structure
  • Communicating network exchanging system and controlling method based on parallel buffer structure
  • Communicating network exchanging system and controlling method based on parallel buffer structure

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Embodiment Construction

[0027] The present invention is described in detail below in conjunction with accompanying drawing:

[0028] The communication network switching system based on the parallel cache structure is characterized in that it includes a cell input 1, a buffer 2, a digital signal processor 3, a crossover switching system 4, and a cell output 5;

[0029] Cell input 1, the input part of the cell, includes N cell ports, and the cell header contains the destination port information of the cell. When the cell is input to the switching system, it first enters the buffer and waits for scheduling and switching;

[0030] Buffer 2, each input port in the parallel buffer structure has N buffers, each buffer can store W cells, and the buffers will notify the neural network scheduling control system 3 of the cell distribution status, and the system will optimize the result Return buffer.

[0031] The digital signal processor 3 is a Hopfield neural network, and the network is composed of N×N neuron...

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Abstract

The invention raises the high efficiency cell dispatching algorithm based on paralleled buffer exchange structure and uses paralleled buffer structure to eliminate the blockage of traffic. The invention consists of cell input, paralleling buffer, interbedded section switch system, cell output and data processor.

Description

technical field [0001] The invention relates to a communication network switching system, in particular to a communication network switching with a parallel cache structure and its control, and belongs to the technical field of communication networks. Background technique [0002] With the rapid development of optical fiber communication technology, especially the continuous maturity of high-density wavelength division multiplexing technology, the bandwidth of the communication network has been rapidly increased, making the switching system of the communication network a bottleneck for the performance improvement of the high-speed communication network. The switching efficiency is of great significance to improve the communication network performance. International-Telecommunication Union Telecommunication Standardization Sector- ITU-T) stipulates that Asynchronous Transfer Mode (ATM) is used as the core and foundation of Broadband Integrated Services Digital Network (B-ISD...

Claims

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Application Information

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IPC IPC(8): H04L12/931
Inventor 常胜江熊涛张便利
Owner NANKAI UNIV
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