Polishing method

a technology of polishing method and polishing plate, which is applied in the direction of lapping machines, manufacturing tools, semiconductor devices, etc., can solve the problems of short circuit, large step height on the surface of the semiconductor device, and complicated structure of the semiconductor element, so as to prevent the effect of being dropped off and damaged
US20060079092A1Inactive Publication Date: 2006-04-13TOGAWA TETABUJI +5
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Patent Information

Authority / Receiving Office
US · United States
Patent Type
Applications(United States)
Current Assignee / Owner
TOGAWA TETABUJI
Publication Date
2006-04-13
Estimated Expiration
Not applicable · inactive patent

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Abstract

The present invention is relates to a polishing method for polishing a semiconductor wafer (W) by pressing the semiconductor wafer (W) against a polishing surface (10) with use of a top ring (23) for holding the semiconductor wafer (W). A pressure chamber (70) is defined in the top ring (23) by attaching an elastic membrane (60) to a lower surface of a vertically movable member (62). The semiconductor wafer (W) is polished while a pressurized fluid is supplied to the pressure chamber (70) so that the semiconductor wafer (W) is pressed against the polishing surface (10) by a fluid pressure of the fluid. The semiconductor wafer (W) which has been polished is released from the top ring (23) by ejecting the pressurized fluid from an opening (62a) defined centrally in the vertically movable member (62).
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Description

[0001] This is a divisional of U.S. application Ser. No. 10 / 481,019, filed May 20, 2004, which was the National Stage of International Application No. PCT / JP03 / 04894, filed Apr. 17, 2003.TECHNICAL FIELD

[0002] The present invention relates to a polishing method, and more particularly to a polishing method for polishing a workpiece, such as a semiconductor wafer having a thin film formed on a surface thereof, to a flat mirror finish. BACKGROUND ART

[0003] In recent years, semiconductor devices have become more integrated, and structures of semiconductor elements have become more complicated. Further, the number of layers in multilayer interconnections used for a logical system has been increased. Accordingly, irregularities on a surface of a semiconductor device become increased, so that step heights on the surface of the semiconductor device tend to be larger. This is because, in a manufacturing process of the semiconductor device, a thin film is formed on the semiconductor device, ...

Claims

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