Compact linked-list-based multi-threaded instruction graduation buffer
a buffer and multi-threaded instruction technology, applied in the field of processors, can solve problems such as multi-threaded processors, data hazard stalls, and structural problems, and achieve the effect of facilitating reading and writing identification values
Inactive Publication Date: 2007-08-30
ARM FINANCE OVERSEAS LTD
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Benefits of technology
[0008] The graduation controller is coupled to the graduation buffer and includes both linked-list head identification registers and linked-list tail identification registers. The linked-list head identification registers and the linked-list tail identification registers facilitate reading and writing identifications values generated by the instruction decode and dispatch unit of the processor to a linked-list data structure associated with a particular program thread. The linked-list head identification registers determine which executed instruction result or results are next to be written to the register file.
Problems solved by technology
As a result, they are subject to control, structural, and data hazard stalls.
More complex processors are typically multi-threaded processors that have out-of-order execution pipelines.
These more complex processors schedule execution of instructions around hazards that would stall an in-order machine.
A shortcoming of this approach, for example, is that it requires a significant amount of integrated circuit chip area to implement N separate buffers.
This approach can also degrade performance in some designs when only a single program thread is running on a multi-threaded processor, for example, if each of the N buffers is limited in size in order to reduce the overall area of the N buffers.
Method used
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[0022] The present invention provides a processor, an instruction graduation unit for a processor, and applications thereof. In the detailed description of the invention that follows, references to “one embodiment”, “an embodiment”, “an example embodiment”, etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
[0023]FIG. 1 illustrates an example processor 100 according to an embodiment of the present invention. As shown in FIG. 1, processor 100 ...
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A processor and instruction graduation unit for a processor. In one embodiment, a processor or instruction graduation unit according to the present invention includes a linked-list-based multi-threaded graduation buffer and a graduation controller. The graduation buffer stores identification values generated by an instruction decode and dispatch unit of the processor as part of one or more linked-list data structures. Each linked-list data structure formed is associated with a particular program thread running on the processor. The number of linked-list data structures formed is variable and related to the number of program threads running on the processor. The graduation controller includes linked-list head identification registers and linked-list tail identification registers that facilitate reading and writing identifications values to linked-list data structures associated with particular program threads. The linked-list head identification registers determine which executed instruction result or results are next to be written to a register file.
Description
FIELD OF THE INVENTION [0001] The present invention relates generally to processors and more particularly to processors having an out-of-order execution pipeline. BACKGROUND OF THE INVENTION [0002] Reduced Instruction Set Computer (RISC) processors are well known. RISC processors have instructions that facilitate the use of a technique known as pipelining. Pipelining enables a processor to work on different steps of an instruction at the same time and thereby take advantage of parallelism that exists among the steps needed to execute an instruction. As a result, a processor can execute more instructions in a shorter period of time. Additionally, modern Complex Instruction Set Computer (CISC) processors often translate their instructions into micro-operations (i.e., instructions similar to those of a RISC processor) prior to execution to facilitate pipelining. [0003] Many pipelined processors, especially those used in the embedded market, are relatively simple single-threaded in-orde...
Claims
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IPC IPC(8): G06F9/30
CPCG06F9/384G06F9/3836G06F9/3851G06F9/3867G06F9/30105
InventorSVENDSEN, KJELD
OwnerARM FINANCE OVERSEAS LTD