Semiconductor device and manufacturing method for the same
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a semiconductor device and manufacturing method technology, applied in the field of semiconductor devices, can solve the problems of reducing production yields, reducing so as to improve the flexibility of wiring layout design, reduce the cost of manufacturing, and improve the efficiency of semiconductor devices.
Inactive Publication Date: 2008-01-31
FUJITSU MICROELECTRONICS LTD
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Abstract
Description
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[0023]In this semiconductor device the first and second wires are connected to at least one of the electrodes over the substrate and first semiconductor element, with the second bump being provided between the first and second wires, thereby preventing deterioration of the bonding portion of the first wire. In addition, it is made possible to prevent adjacent wires from contacting each other, particularly short-circuits due to contact in cases where they are arranged so as to intersect, thereby achieving increased flexibility in designing a wiring layout. Accordingly, high-density wiring can be realized and the resulting semiconductor device is small and of high performance.
[0025]Also in this semiconductor device, the first and second wires are connected to at least one of the electrodes over the base and first semiconductor element, with the second bump being provided between the first and second wires, thereby not only preventing deterioration of the bonding portion of the first wire, but also preventing adjacent wires from contacting each other. Thus, increased flexibility can be achieved upon designing of a wiring layout.
[0027]In this method, the semiconductor element having the electrode on its surface is first provided on the substrate having the electrode on its surface. The first wire is then connected through the first bump to at least one of the electrodes over the substrate and semiconductor element. As a result, contact between adjacent wires is prevented to achieve increased flexibility in designing a wiring layout. In particular, short-circuits due to contact between adjacent wires can be prevented in cases where they are arranged so as to intersect. Thus, it is made possible to achieve efficient manufacture of a semiconductor device with high-density wiring.
Problems solved by technology
Too long wires result in difficulty in controlling the formation of stable wire loops and, therefore, adjacent wires may be brought in contact with each other upon wiring, undesirably reducing production yields.
Moreover, miniaturization (slimming down) of the semiconductor device cannot be achieved due to increased wire loop height.
Furthermore, the wires are susceptible to deformation.
For this reason, when the wires are to be encapsulated in resin, flowing resin causes adjacent wires to contact each other, resulting in malfunction of the resulting semiconductor device.
However, wire bonding used to achieve this configuration causes problems described below.
Specifically, JP-A Nos. 04-142073, 06-37250 and 11-204720 fail to disclose a specific wiring layout (i.e., the loop shape and method of forming wires) and it appears that the likelihood that adjacent wires contact upon wire formation is high.
This strategy, however, has a problem that in a case where the second bonding end of the second wire is to be formed on or next to the second bonding end of the first wire on the bump, the bonding capillary undesirably touches the second bonding end of the first wire, which has been formed previously, upon second bonding of the second wire to thereby cause connection deterioration of the second bonding end of the first wire.
This sometimes makes wire-bonding operations difficult.
In addition, if adjacent wires intersect, there will be a problem that the resulting semiconductor device may not operate normally due to contacting wires.
Method used
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example 1
[0066]FIG. 1 shows First Example of the semiconductor device of the present invention.
[0067]A semiconductor device 100 in this Example is a so-called ball grid array (BGA) semiconductor device.
[0068]This semiconductor device 100 has two stacked semiconductor chips (semiconductor elements) 11A and 11B arranged on the upper surface of a substrate; the semiconductor chip 11A is bonded to the substrate with an adhesive 12A, and the semiconductor chip 11B is bonded to the semiconductor chip 11A with an adhesive 12B.
[0069]This multi-chip stacked package is used to allow a semiconductor device to offer multifunctionality achieved by the combined use of different semiconductor chips, high performance achieved by an increased memory storage capacity, etc.
[0070]Electrodes (also referred to as “electrode pads”) 21 formed by so-called photo-etching, selective plating or the like are selectively arranged over the upper surface of the substrate 10 at positions close to the semiconductor chip 11A....
first modification of example 1
[0098]The following modification can be made to the semiconductor device 100 of Example 1.
[0099]That is, a so-called lead frame structure may be adopted in stead of the substrate 10.
[0100]In a semiconductor device 150 there are stacked semiconductor chips 11A and 11B provided on a die pad 15A of a lead frame 15.
[0101]The die pad 15A, an inner lead 15B of the lead frame 15, and the semiconductor chips 11A and 11B are sealed with sealing resin 13 while encapsulating wires 41 and 42.
[0102]In this configuration one end of the wire 41 is allowed to have a ball-shaped portion B and connected to the inner lead 15B of the lead frame 15 by means of so-called ball bonding, and the other end is connected to a bump 31 by means of stitch bonding, which is arranged on the electrode 22 selected on the semiconductor chip 11A.
[0103]A bump 32 is then arranged on the stitch-bonding portion S of the wire 41.
[0104]One end of the wire 42 is also allowed to have a ball-shaped portion B and connected to th...
second modification of example 1
[0106]FIG. 3 shows a semiconductor device configuration where two wires (i.e., the wires 41 and 42) are connected to the electrode 22 in reverse order to the order in which they are connected in the semiconductor device 100 of Example 1.
[0107]More specifically, using the wire 42, the electrode 22 arranged on the semiconductor chip 11A is first connected to the electrode 23 arranged on the semiconductor chip 11B. Thereafter, using the wire 41, the electrode 21 arranged on the substrate 10 is connected to the electrode 22 arranged on the semiconductor chip 11A.
[0108]In this procedure, the other end of the wire 42 is first stitch-bonded to the bump 31 arranged on the electrode 22, the bump 32 is arranged on the resulting stitch-bonding portion S, and the other end of the wire 41 is stitch-bonded to the bump 32.
[0109]One end of the wire 42 is connected to the electrode 23 by means of ball bonding, which is arranged on the semiconductor chip 11B. One end of the wire 41 is connected to th...
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Abstract
To provide a small, high-performance semiconductor device in which contact between adjacent wires is prevented for increased flexibility in designing a wiring layout, and an efficient method for manufacturing the semiconductor device. The semiconductor device includes a substrate 10 having an electrode 21A arranged on its surface; and a first semiconductor element 11A which includes an electrode 22 arranged on its surface and which is supported by the substrate 10, wherein a first wire 41 is connected through a first bump 31 to at least one of the electrodes over the substrate 10 and semiconductor element 11A (i.e., at least one of the electrodes 21 and 22), and a second wire 42 is connected through a second bump 32 to a bonding portion of the wire 41.
Description
CROSS-REFERENCE TO RELATED-APPLICATIONS[0001]This application is based upon and claims the benefits of the priority from the prior Japanese Patent Application No. 2006-205381 filed on Jul. 27, 2006, the entire contents of which are incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to a semiconductor device and a manufacturing method for the same. More specifically, the present invention relates to a semiconductor device in which contact between adjacent wires is prevented for increased flexibility in designing a wiring layout, and to an efficient method for manufacturing the same.[0004]2. Description of the Related Art[0005]Conventionally, electrical connecting between adjacent electrodes in a semiconductor device sometimes involves connection of a plurality of wires to one electrode formed on a semiconductor chip, or a semiconductor element (e.g., see Japanese Patent Application Laid-Open UP-A) Nos. 04-142...
Claims
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Application Information
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Patent Type & AuthorityApplications(United States)
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