Time Delay Compensation Circuit Comprising Delay Cells Having Various Unit Time Delays

Abstract

A time delay compensation circuit comprises delay cells having various unit time delays. A delay-locked loop, a type of the time delay compensation circuit, includes a phase detector, a delay line, and a filter unit. The phase detector compares the phase of the external clock signal with that of the feedback clock signal and outputs a phase difference as an error control signal. The delay line includes a plurality of delay cells having various unit time delays. The number of delay cells is adjusted in response to a predetermined shift signal. The delay line receives the external clock signal and outputs an output clock signal, which is obtained by controlling the phase of the external clock signal. The filter unit generates the shift signal, which selects the number of delay cells in the delay line, in response to the error control signal. In the time delay compensation circuit, the front delay cells, which are used to compensate for a delay of an external clock signal having a high frequency, have short unit time delays so as to reduce jitter due to quantization error. Also, the rear delay cells, which are used to compensate for a delay of the external clock signal having a low frequency, have long unit time delays so as to reduce the number of delay cells required for the delay compensation.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This application is a divisional application of U.S. application Ser. No. 10 / 716,146 filed on Nov. 18, 2003, the disclosure of which is herein incorporated by reference in its entirety. U.S. application Ser. No. 10 / 716,146 claims the priority of Korean Patent Application No. 2002-78392, filed on Dec. 10, 2002, in the Korean Intellectual Property Office.BACKGROUND OF THE INVENTION[0002]1. Technical Field[0003]The present invention relates to time delay compensation circuits, and more particularly, to a time delay compensation circuit comprising delay cells having various unit time delays.[0004]2. Discussion of the Related Art[0005]In an I / O interface where data is transmitted in synchronization with a clock signal, as the load on a data bus is increased and the frequency of the clock signal becomes higher, it becomes more difficult to correctly synchronize the clock signal with the data. That is, the data needs to be correctly synchronized ...

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