Stacked-type semiconductor device package

a semiconductor device and stacking technology, applied in semiconductor devices, semiconductor/solid-state device details, electrical equipment, etc., can solve the problems of high-level technology for the integration of memory chips, difficult to improve the production yield of these types of packages, and complex process

Inactive Publication Date: 2010-01-21
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This configuration reduces package thickness, increases mounting density, and enhances mechanical and electrical reliability, thereby improving production yield and reducing manufacturing costs by enabling the stacking of semiconductor chip packages with different structures and sizes without the need for solder balls.

Problems solved by technology

However, the increased integration of the memory chip requires high-level technology such as precise ultra-small linewidth processes as well as significant development time.
Therefore, it is difficult to improve production yield of these types of packages.
In addition, a process becomes complex when semiconductor chip packages having different structures or sizes are stacked by means of a POP method using solder balls.

Method used

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  • Stacked-type semiconductor device package
  • Stacked-type semiconductor device package
  • Stacked-type semiconductor device package

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Embodiment Construction

[0019]The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown.

[0020]FIG. 1A is a top plan view illustrating a semiconductor chip package according to an embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along the line I-I′ of FIG. 1A.

[0021]Referring to FIGS. 1A and 1B, a semiconductor chip package 100 may include a semiconductor chip 110, a printed circuit board (PCB) 120, and a molding material 130.

[0022]The semiconductor chip 110 may include bonding pads 112 and sector-form molding electrodes 114 disposed so as to cover the bonding pads 112, respectively. The bonding pads 112 and the molding electrodes 114 are provided on an active surface of the semiconductor chip 110. The molding electrodes 114 may be formed by separating a semiconductor wafer into semiconductor chips 110 after forming a conductive molding material, such as copper (Cu) ...

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Abstract

A stacked-type semiconductor device package is provided. The stacked-type semiconductor device package includes a plurality of stacked semiconductor chip packages with joining electrodes exposed on sides of the semiconductor chip packages and a flexible printed circuit board (flexible PCB) on which the stacked semiconductor chip packages are mounted. The flexible PCB includes a first surface having connecting electrodes corresponding to the joining electrodes of the stacked semiconductor chip packages and a second surface opposite the first surface. The flexible PCB covers the sides of the stacked semiconductor chip packages, and the connecting electrodes of the first surface are connected to the joining electrodes of the stacked semiconductor chip packages.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is a Continuation of U.S. patent application Ser. No. 11 / 961,747, filed on Dec. 20, 2007, now pending, which claims priority under 35 U.S.C. §119 from Korean Patent Application No. 10-2006-131082 filed on Dec. 20, 2006, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by referenceBACKGROUND[0002]1. Technical Field[0003]The present invention relates to semiconductor device packages and, more particularly, to a stacked-type semiconductor device package.[0004]2. Description of the Related Art[0005]In the semiconductor industry, packaging technologies for integrated circuits (ICs) have been advancing to meet requirements for miniaturization and mounting reliability. For example, the requirement for miniaturization results in acceleration of technological development for a package having a similar size in relation to a semiconductor chip. Further, the requirement for mounting rel...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): H01L25/11
CPCH01L23/24H01L23/5387H01L25/105H01L2225/1023H01L2225/1064H01L2225/107H01L2224/16225H01L2224/73265H01L2224/48227H01L2224/32225H01L2924/00012H01L24/73H01L2924/14H01L2924/00H01L23/12
InventorEUN, HYUNG-LAE
OwnerSAMSUNG ELECTRONICS CO LTD