ATM switching system connectable to I/O links having different transmission rates

Abstract

An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and / or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.

Description

BACKGROUND OF THE INVENTIONThe present invention relates to a switching system, or more in particular to an ATM (Asynchronous Transfer Mode) switching system used with the speech path equipment of a wide-bandwidth ISDN exchange and, especially, an ATM switching system suitable for accommodating a plurality of types of input-output links having different transmission rates.A "TDM Switching System" proposed by JP-A-59-135994 is known, for example, as an ATM switching system applied to the wide-bandwidth ISDN exchange.This switching system comprises a multiplexer for multiplexing a fixed-length packet (hereinafter referred to as "the cell") inputted from each input line, a buffer memory for inputting a multiplexed cell, a demultiplexer for periodically separating the cells outputted from the buffer memory among output lines, and a buffer memory control circuit for controlling the buffer memory for each output line. The buffer memory control circuit, which includes FIFO (First In First ...

AI Technical Summary

Benefits of technology

Another object of the present invention is to provide an ATM switching system which can accommodate output lines of a plurality of different transmission rates including, say, 600 Mbps, 150 Mbps and 50 Mbps with a comparative freedom.

In an ATM switching system according to the present invention, assuming that the internal links connected to the output ports of the switch unit are set to the same transmission rate and that the output cells from the internal output links are bundled together by a multiplexer (a kind of conversion means), for example, the cell transmission rate at the output lines connected to the multiplexer can be increased. On the other hand, the output cell from an internal output link may be distributed among a plurality of output lines by a demultiplexer (a kind of conversion means) thereby to reduce the cell transmission rate at each output line. Assuming that a quadruple multiplexer is installed for an internal output link having a transmission rate of 150 Mbps, for example, it is possible to realize an output line having a transmission rate of 600 Mbps. Also, an output line having a transmission rate of 50 Mbps is realized by providing a demultiplexer of three divisions.

According to the present invention, the output ports of the switch unit are set to the same cell transmission rate and a new speed change means (multiplexer or demultiplexer) is added between the output port and the output link or is replaced with other appropriate means in accordance with the transmission rate required by the output link thereby to enable comparatively free selection of cell transmission rate on each output line. In this case, with regard to the control system of the ATM switching system, the contents of the control table are simply modified by external microcomputer control or the like means. Thus the transmission rate of the output lines can be easily changed.

Problems solved by technology

When an attempt is made to accommodate a plurality of types of output links (output lines) different in transmission rate in a switching system having the above-mentioned configuration, therefore, the problem is posed of a very complicated hardware configuration of the buffer memory control circuit.

Images