Firewall chip data packet buffer management method

Abstract

The invention discloses a method for managing the data packet caching of a firewall chip, which comprises the following steps: a memory is distributed in the inner of the chip; the memory is also divided into a plurality of plates with same size and each plate can store a data packet. A tag queue of free memory is built and each lag correspondingly stores an initial address of the data packet plate. If a data packet enters, a lag is taken form the tag queue of the free memory. The data packet is stored into the data packet plate according to the initial address of the data packet plate indicated by the lag; an analysis data packet builds a data packet lag; a process module which determines to process the data packet writes the data packet lag into the data lag queue of the module; the module takes out the data packet lag from the data packet lag queue of the module and carries out a corresponding process according the content of the data packet lag to realize the function possessed by a common firewall. The invention avoids the frequent flitting of the data packet inside the chip, thus enhancing process efficiency of the data packet.

Description

technical field [0001] The invention relates to network security and networking technologies, in particular to a data packet cache management method of a firewall chip. Background technique [0002] With the continuous development of network technology, people have higher and higher requirements for network response speed, data packet throughput and network security, and a security firewall with small delay and large traffic is required. This requires a chip (FPGA / ASIC) to achieve hardware acceleration and improve the performance of the firewall. The chip mainly realizes the parsing, filtering and forwarding of sending and receiving data packets. This requires buffer management of packet buffers entering and leaving the chip. [0003] At present, the method used by the firewall acceleration chip to realize data packet cache management is: each internal processing module is assigned a piece of memory to store data packets to be processed, and the processing module takes out ...

AI Technical Summary

Problems solved by technology

This method of data packet cache management is relatively simple, but the data packets are moved multiple times in the memory, which is inefficient and takes up a lot of memory, and each data packet takes a long time to process in the chip

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