Method and device for improving virtual concatenation delay compensation caching efficiency in synchronous digital hierarchy

A technology of synchronous digital system and delay compensation, which is applied in the field of communication, can solve the problems of high overhead time, low compensation cache efficiency, complex operation sequence, etc., and achieve the effect of reducing useless overhead and improving efficiency

Inactive Publication Date: 2010-02-24
ZTE CORP
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Problems solved by technology

That is, due to the complex operation sequence of SDRAM, it may take a lot of overhe

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  • Method and device for improving virtual concatenation delay compensation caching efficiency in synchronous digital hierarchy
  • Method and device for improving virtual concatenation delay compensation caching efficiency in synchronous digital hierarchy
  • Method and device for improving virtual concatenation delay compensation caching efficiency in synchronous digital hierarchy

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Embodiment Construction

[0036] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be further described in detail below in conjunction with the embodiments and the accompanying drawings. Here, the exemplary embodiments and descriptions of the present invention are used to explain the present invention, but not to limit the present invention.

[0037] Embodiments of the present invention provide a method for delay compensation and alignment buffering of multipath transmitted VC members at the receiving end of VCG in SDH equipment, by establishing a corresponding relationship between the multiplexing path of VC and the Bank storage area in SDRAM, According to the VC multiplexing relationship, the read and write operation requests of each VC are polled and dispatched to the SDRAM controller for processing. The characteristics of concurrent operations in different Bank areas of SDRAM can be used...

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Abstract

The invention discloses a method and a device for improving virtual concatenation delay compensation caching efficiency in a synchronous digital hierarchy, which belong to the technical field of communications. The method comprises the following steps: mapping at least four virtual containers VCs into four banks of a synchronous dynamic random access memory SDRAM respectively; writing a synchronous dynamic random access memory SDRAM write request into write request first in first out FIFO registers of the VCs respectively; writing a synchronous dynamic random access memory SDRAM read request into read request first in first out FIFO registers of the VCs respectively; and polling the write request FIFO registers and read request FIFO registers of the VCs; therefore, unnecessary overhead of SDII operation is reduced and the virtual concatenation delay compensation caching efficiency in the SDH is improved.

Description

technical field [0001] The present invention relates to the field of communication technology, in particular to a method and device for improving VCG (Virtual Concatenation Group, Virtual Concatenation Group) delay compensation buffer efficiency in SDH (Synchronous Digital Hierarchy, Synchronous Digital Hierarchy) equipment. Background technique [0002] As the mainstream equipment of the current transport network, SDH equipment has been widely used in the communication field. Its standard VC12 (low-order virtual container), VC3 (high-order virtual container), and VC4 (high-order virtual container) containers can be used to carry E1, E3 / T3, E4 and other fixed-bandwidth TDM (time division multiplexing) services, so the demand for VC (Virtual Container, virtual container) cascading is not strong, but with the rapid development of data services, SDH equipment carries data services become a problem that must be solved. [0003] One of the characteristics of data services is the...

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Application Information

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IPC IPC(8): H04J3/16
CPCH04J3/0623H04J2203/0094G06F12/00H04J3/00
Inventor 冯景斌
Owner ZTE CORP
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