Link layer controller of IEEE1394 bus

A technology of link layer and controller, which is applied in the direction of bus network, data exchange through path configuration, electrical components, etc. It can solve the problems that aerospace-grade devices are not easy to obtain, and achieve good versatility and high performance.

Inactive Publication Date: 2010-06-30
CENT FOR SPACE SCI & APPLIED RES
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Realized by using high-grade FPGA devices, or after tape-out of ASIC with radiation-resistant technology, the controller can be used in aerospace electronic equipment, solving the problem that aerospace-grade devices of IEEE1394 bus are not easy to obtain

Method used

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  • Link layer controller of IEEE1394 bus
  • Link layer controller of IEEE1394 bus
  • Link layer controller of IEEE1394 bus

Examples

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Embodiment Construction

[0040] The present invention will be described in detail below with reference to the accompanying drawings.

[0041] like figure 1 As shown, the present invention is composed of five basic modules: host interface, high-speed data interface, data buffer and routing, link layer core module and configuration register.

[0042] The host interface part provides a common 16-bit CPU interface, through which the timing cooperation with different CPUs can be realized. The host interface module is internally connected with the configuration register, data buffer and routing control module through a 16-bit bidirectional data bus and some control lines. The external CPU can use this interface to read and write the internal configuration registers of the link layer controller, and perform access operations on the data buffer: write data packets to be sent or read received data packets. The timing of the host interface is completed under the control of the clock signal provided by the ext...

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Abstract

The invention relates to a link layer controller of an IEEE1394 bus, which comprises a host computer interface, a link layer core module, a data buffering and routing control module, a high-speed data interface module and a configuration register, wherein an external CPU (central processing unit) can read and write data buffering areas in the configuration register and the access data buffering and routing control module by the host computer interface; the data buffering and routing control module is positioned among the link layer core module and the host computer interface and a high-speed data interface, used for providing the switching control among different data receiving and sending channels and also provided with two asynchronous first-in first-out memories which are respectively used for the buffering of receiving and sending data and the synchronization of cross-clock domain data; and the configuration register is used for providing initial configuration and control for the link layer core module and the data buffering and routing control module and controlling and acquiring the working states of all modules of the link layer controller by the host computer interface reading and writing configuration register, and has good portability.

Description

technical field [0001] The invention relates to the design of a computer standard serial bus—IEEE1394 bus protocol controller, in particular to a link layer controller of the IEEE1394 bus used in the field of space electronics technology. Background technique [0002] In electronic systems, in order to simplify hardware circuit design and optimize system structure, a group of lines is commonly used, configured with appropriate interface circuits, and connected to various components and peripheral devices. This group of shared connection lines is called a bus. Adopting the bus structure facilitates the expansion of components and equipment, especially the unified bus standard is formulated, which makes it easier to realize the interconnection between different equipment. Advanced bus technology has a very important impact on improving the performance of electronic systems. [0003] In the early spacecraft, the bus structure was not used. The communication between the compute...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L29/06H04L12/40
Inventor 周庆瑞孙辉先陈晓敏凡启飞曹松
Owner CENT FOR SPACE SCI & APPLIED RES
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