Structure and inhibited operation of flash memory with split gate

Abstract

A method of performing a reading operation to a memory device including a plurality of flash memory cells. The method includes applying a first voltage bias to a control gate of a selected memory cell in the flash memory array and applying a second voltage bias to a word line of the selected memory cell. A control gate of an unselected memory cell in the flash memory array is grounded and a third voltage bias is applied to a word line of the unselected cell to turn off a word line channel of the unselected memory cell. The selected memory cell and unselected memory cell are configured in the memory device and are connected to different word lines. The first voltage bias and the second voltage bias have a same polarity. The third voltage bias and the second voltage bias have opposite polarities.

Description

technical field [0001] This specification mainly deals with the technology of flash memory. Background technique [0002] A conventional flash memory device has a memory array including many memory cells arranged in blocks. Each memory cell has a field effect transistor including a control gate and a floating gate. The floating gate stores charge and the source and drain regions are separated in the body by an oxide. Each memory cell can be electrically charged by injecting electrons into the floating gate. Under an erase operation, charge can be removed from the floating gate by tunneling to the source region or the erase gate. The determination of the data stored in the flash memory unit can be determined according to the presence or absence of charges on the floating gate. [0003] Considering packing density and cost, reducing the size of memory elements is a trend. In general flash memory structures, the need to shorten the word line length due to conflicting facto...

AI Technical Summary

Problems solved by technology

For split gate flash memory devices, shortening the word line length results in higher channel current leakage and increased bit errors

If the channel length is increased in order to improve channel current leakage, it will cause a drop in read current during erase operations and affect the endurance window after operating cycles.

Additionally, current leakage can cause errors in reading

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