Full parallel input quasi-cyclic matrix multiplier based on ring shift left in DTMB

A technology of quasi-circular matrix and cyclic left shift, which is applied in the field of channel coding, can solve the problems of high power consumption, low throughput, and high cost of the circuit, so as to improve the operating frequency and throughput, reduce registers and delays, and reduce power consumption and cost effects

Inactive Publication Date: 2014-07-16
RONGCHENG DINGTONG ELECTRONICS INFORMATION SCI & TECH CO LTD
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Problems solved by technology

[0022] In order to be compatible with 3 kinds of code rates, the existing solution of the quasi-circular matrix multiplier with full parallel input in the DTMB standard multi-code rate QC-LDPC approximate lower triangular coding has two shortcomings: one is that 381 register...

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  • Full parallel input quasi-cyclic matrix multiplier based on ring shift left in DTMB
  • Full parallel input quasi-cyclic matrix multiplier based on ring shift left in DTMB
  • Full parallel input quasi-cyclic matrix multiplier based on ring shift left in DTMB

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Embodiment Construction

[0029]The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, so as to define the protection scope of the present invention more clearly.

[0030] make with are the generating polynomials f i,j The result of a rotate right by n bits and a rotate left by n bits, where 0≤n≤b. Then, the i-th item on the right side of the equation (7) can be expanded as

[0031] m i F i , j = e i × b f i , j r ( 0 ) + ...

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Abstract

The invention provides a full parallel input quasi-cyclic matrix multiplier based on ring shift left in a DTMB, wherein the multiplier is used for achieving multiplication of vectors m and quasi-cyclic matrixes F in DTMB standard multiple rate QC-LDPC approximate lower triangular codes. The multiplier comprises three generator polynomial lookup tables for prestoring all circulant matrix generator polynomials in the matrixes F, three 127-bit binary multipliers for carrying out scalar multiplying on vector fields of the m and generator polynomial bits, 127 4-bit binary adders for carrying out modulor-2 addition on products and shifting register content, and a 127-bit shifting register for storing the sum of results obtained after 1-bit ring shift left is carried out. The full parallel input multiplier is compatible with all code rates and has the advantages that the number of the registers is small, power consumption is little, cost is low, work frequency is high and the handling capacity is large.

Description

technical field [0001] The invention relates to the field of channel coding, in particular to a cyclic left-shift quasi-circular matrix multiplier with full parallel input in DTMB standard multi-code rate QC-LDPC approximate lower triangular coding. Background technique [0002] Low-Density Parity-Check (LDPC) code is one of the efficient channel coding techniques, and Quasi-Cyclic LDPC (QC-LDPC) code is a special LDPC code. Both the generation matrix G and the check matrix H of the QC-LDPC code are arrays composed of circulant matrices, which have the characteristics of a segmented cycle, so they are called QC-LDPC codes. The first row of the circulatory matrix is ​​the result of the cyclic right shift of the last row by 1 bit, and the remaining rows are the result of the cyclic right shift of the previous row by 1 bit; the first column of the circulatory matrix is ​​the result of the cyclic shift of the last column by 1 bit, and the remaining columns They are all the resu...

Claims

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Application Information

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IPC IPC(8): H03M13/11
Inventor 张鹏刘志文张燕
Owner RONGCHENG DINGTONG ELECTRONICS INFORMATION SCI & TECH CO LTD
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