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DDR3 arbitration controller and method for high-speed ccd data storage

An arbitration controller, DDR3 technology, applied in the direction of image memory management, etc., can solve the problems of complex interface configuration, mismatching read and write speed, etc., and achieve the effect of high integration, saving design space, and simple interface

Inactive Publication Date: 2017-09-22
NANJING UNIV OF SCI & TECH
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  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

DDR3 has been very mature as a memory technology for notebooks. Due to the fast working speed of DDR3, it is more suitable for high-speed storage, small in size, easy to integrate, and low in power consumption. The external memory of high-speed CCD has also begun to use DDR3, but the interface used by DDR3 The configuration is complicated, the data flow speed of the CCD front-end to the memory does not match the read and write speed of DDR3, etc. To use DDR3 as an external memory in a high-speed CCD system, it is necessary to solve problems such as interface configuration and speed matching.
But there is no good solution in the prior art

Method used

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Embodiment Construction

[0029] A DDR3 arbitration controller of the present invention includes a read-write control module, a DDR3 arbitration module, an IP core control module, a data format replacement module, and a read-write storage module. The IP core control module is mainly responsible for driving the read-write storage module, so that the read-write storage module can read and write data correctly. The read-write storage module is mainly responsible for matching the data flow provided by the front-end with the read-write speed of the read-write storage module. The read-write speed of the read-write storage module is as high as hundreds of megabytes. The front-end data stream cannot reach this speed, and subsequent modules cannot. Such a fast speed is required, so the data written into the read-write storage module and the data read from the read-write storage module must be matched in speed. The arbitration module is mainly responsible for arbitrating the order of applications when multiple d...

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Abstract

DDR3 arbitration controller and method for high-speed CCD data storage. A DDR3 arbitration controller of the present invention includes a read-write control module, a DDR3 arbitration module, an IP core control module, a data format replacement module, and a read-write storage module. The IP core control module is mainly responsible for driving the read-write storage module, so that the read-write storage module can read and write data correctly. The read-write storage module is responsible for matching the data stream given by the front-end with the read-write speed of the read-write storage module. The read-write speed of the read-write storage module is much faster than the front-end data stream and the data stream required by the subsequent circuit, so data is written to read and write The memory module and the data read from the read-write memory module must be speed-matched. The arbitration module is responsible for arbitrating the order of applications when multiple data streams apply for the use of the read-write storage module, determining the response order, and allocating resources for the use of the read-write storage module. The data format conversion module is responsible for converting the data format read from the read-write storage module into the standard format required by subsequent modules.

Description

technical field [0001] The invention belongs to the field of high-speed CCD image storage, in particular to a DDR3 arbitration controller and method for high-speed CCD data storage. Background technique [0002] In the video image display of high-speed CCD, some algorithms will use external memory, and the external memory used in the past is SRAM, because SRAM is easy to use, and the use technology of SRAM is close to maturity at present. As the external memory of CCD, the current technology of SRAM can reach the highest operating frequency of 167M, which cannot meet the storage requirements of high-speed CCD. At the same time, SRAM is limited by the technology of chip manufacturing, and its volume can no longer be reduced, and its integration level is low, so it cannot meet the development requirements of miniaturized CCD. In addition, the power consumption of SRAM is relatively large, which is also a problem that cannot be solved by the current technology, so SRAM cannot ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06T1/60
Inventor 陈钱尹春梅顾国华隋修宝高航孙镱诚
Owner NANJING UNIV OF SCI & TECH
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