16 results about "Read-write memory" patented technology

The invention provides a hydrogen energy management system and a control method thereof, and the method comprises the steps: controlling a hydrogen production / charging device to enter a hydrogen charging mode in response to a hydrogen charging instruction for the hydrogen production / charging device; reading a readable / writable memory of the hydrogen storage device to obtain the initial hydrogen content of the hydrogen storage device and displaying the initial hydrogen content on a first display module; the current hydrogen content of the hydrogen storage device is obtained and written into a readable / writable memory when the hydrogen charging increment is at an interval of a hydrogen charging increment threshold value, and the readable / writable memory is read to obtain the current hydrogen content and display the current hydrogen content on a first display module when the hydrogen charging time is at an interval of a hydrogen charging time threshold value; when the hydrogen charging increment reaches a preset hydrogen charging threshold value, the hydrogen production / charging device is controlled to stop charging hydrogen into the hydrogen storage device, the current hydrogen content and the number of times of hydrogen charging are obtained and written into the readable / write memory to be fed back to the server, and the hydrogen production / charging device is controlled to exit the hydrogen charging mode. After the technical scheme is adopted, the hydrogen energy device can be monitored in real time, accurately controlled and calibrated, and the hydrogen energy management efficiency is improved.

The application discloses an electric read-write memory device based on 180-degree flip of anti-ferromagnetic Neel vector, a preparation method and a read-write method. The electric read-write memory device comprises a substrate layer, an anti-ferromagnetic layer and a spin source layer which are sequentially stacked from bottom to top and constitute a heterostructure. The material of the substrate layer is a single crystal wafer capable of epitaxially growing the anti-ferromagnetic layer. The material of the anti-ferromagnetic layer is a collinear anti-ferromagnetic material with abnormal Hall effect or a staggered magnet with abnormal Hall effect. The material of the spin source layer has a spin current generation capability. The memory utilizes a current pulse to drive 180-degree flip of the Neel vector. The Neel vector before and after the 180-degree flip has two abnormal Hall resistance states of high and low, and can be used for storing information "0" and "1". The application not only enriches the connotation of the interaction between the spin current and the anti-ferromagnetic Neel vector, but also lays a foundation for constructing a high-density, high read-write speed and low-power nonvolatile magnetic random memory.

A serial read write memory is provided in which a write driver logic circuit controls a write driver to drive the bit lines in a selected column responsive to a binary value of a data in signal during a write operation in which a write mask signal is not asserted. Should the write mask signal be asserted, the write driver logic circuit controls the write driver to charge the bit line in the selected column and then to float the bit lines regardless of the binary value of the data in signal during a write operation.

A serial read write memory is provided in which a write driver logic circuit controls a write driver to drive the bit lines in a selected column responsive to a binary value of a data in signal during a write operation in which a write mask signal is not asserted. Should the write mask signal be asserted, the write driver logic circuit controls the write driver to charge the bit line in the selected column and then to float the bit lines regardless of the binary value of the data in signal during a write operation.

The invention belongs to the technical field of power line carrier communication, and relates to a power line carrier communication data processing method, a processor, a communication terminal and a system. The data polls are distributed and stored to four single-port read-write memories, and binary representation of the initial address index of each data is obtained; calculating the number of iteration layers of the radix-4 FFT, the number of butterfly operation groups in each layer of iteration, and the inter-butterfly data index difference and the intra-butterfly data index difference in each layer of iteration; rounding down the quotient of the initial address index of each data and the intra-butterfly data index difference in each layer of iteration to obtain a loop right shift value, and adding the binary representation of the initial address index and the binary representation of the loop right shift value to obtain the binary representation of the target address index of each data in each layer of iteration; therefore, each piece of data is stored in the single-port read-write memories according to the target address index, and four pieces of data to be processed are read in parallel from the four single-port read-write memories according to a fast Fourier transform rule so as to carry out fast Fourier transform.

This application provides a flight time statistics device, method, and laser ranging system. The statistics device includes a dual-port read / write memory and a single-port read / write memory. The dual-port read / write memory stores a first accumulated data set for the current integration period. The first accumulated data set includes first accumulated photon count values ​​for M flight times, where the first accumulated photon count value for each flight time is the sum of the K-1 initial photon count values ​​corresponding to the flight time within the first K-1 statistical periods of the K statistical periods of the current integration period. The single-port read / write memory stores a second accumulated data set in the Kth statistical period. The second accumulated data set includes second accumulated photon count values ​​for M flight times, where the second accumulated photon count value for each flight time is the sum of the first accumulated photon count value for the flight time and the initial photon count value corresponding to the Kth statistical period. This addresses the technical problem of the large size of laser ranging systems.

The present invention provides a dual-processor communication system, including a main controller, an auxiliary controller, and a read-write memory. The auxiliary controller is configured to execute an internally stored program to implement the following steps: receiving a UART data packet sent by the main controller via a UART; reading the value of the corresponding address of the read-write memory via an I2C bus interface to determine whether the value of the corresponding address of the read-write memory matches the address of the read-write memory; if not, returning an error code to the main controller via the UART; if so, performing data acquisition according to control instructions to obtain acquired data; reporting the acquired data to the main controller based on the read-write memory data, and adjusting the current state based on the read-write memory data. This system aims to address the problems of existing dual-processor devices, such as frequent communication that occupies processor resources; data exchange that is prone to anomalies due to interference; and the need to reinitialize the original MCU control and state changes after a CPU failure restart.

A static random-access memory is provided with a double-pumped operation in which a read operation to a multiplexed group of columns of bitcells may occur in a first portion of a memory clock cycle and in which a write operation to a write-selected column in the multiplexed group of columns of bitcells may occur in a second portion of the memory clock cycle. The write operation to the write-selected column occurs without any precharging of bit lines in the write-selected column during read and write operations.

The present invention provides a gaming machine that can initialize the main RAM for both the working area within the used area and the working area outside the used area. [Solution] The gaming machine of the present invention has an initialization means for initializing a predetermined range of a read / write memory. The read / write memory consists of a first storage means for storing data directly related to the progress of the game and a second storage means for storing data not directly related to the progress of the game. The initialization start position of the first storage means is represented by a 2-byte address, and the final initialization position is set as a fixed address, one for each of the first and second storage means. The initialization means stores the value of the 2-byte address related to the initialization start position in a storage determination area, and can determine the address of the initialization start position of the second storage means according to the value of the lower address of the address.

A static random access memory is provided with dual pump operations in which read operations to a multiplexed column group of bit cells can occur in a first portion of a memory clock cycle and in which write operations to a write select column of the multiplexed column group of bit cells can occur in a second portion of the memory clock cycle. The write operations to the write select column occur during the read and write operations without any pre-charge of bit lines in the write select column.

The utility model provides a memory data read-write device which comprises a positioning assembly and a data read-write unit, the positioning assembly comprises a base, a first spring ejector pin and a second spring ejector pin, the base is provided with a positioning groove used for positioning a to-be-read-written memory, the first spring ejector pin is used for abutting against a contact of a first face of the to-be-read-written memory, and the second spring ejector pin is used for abutting against a second face of the to-be-read-written memory. The second spring ejector pin is used for abutting against a contact of a second surface of the memory to be read and written; the first spring ejector pin and the second spring ejector pin are both in communication connection with the data read-write unit, and the data read-write unit performs data read-write on the to-be-read-write memory through the first spring ejector pin and the second spring ejector pin. According to the memory data read-write device provided by the invention, the positioning of the memory is realized through the positioning assembly, the data read-write of the memory is realized through the communication connection between the spring ejector pin and the data read-write unit, the data read-write of the memory can be quickly carried out, and the production efficiency is improved.

The present application discloses a library file encryption method, a library file decryption method, and a library file encryption device. The method encrypts a library file using a public key to form an encrypted library file; obtains the application's call information for the encrypted library file and generates interface information; saves the encrypted library file and the interface information into a firmware file respectively; and burns the firmware file into a readable and writable memory inside or external to the SoC chip, so that when the firmware file is loaded into the random access memory inside or external to the SoC chip, the encrypted library file is decrypted using a private key to obtain the decrypted library file. While allowing the external release of library files, the present application prevents the contents of the library files from being leaked. It can not only ensure the convenience and efficiency of secondary development using library files, but also improve the security of library files.

A static random-access memory is provided with a double-pumped operation in which a read operation to a multiplexed group of columns of bitcells may occur in a first portion of a memory clock cycle and in which a write operation to a write-selected column in the multiplexed group of columns of bitcells may occur in a second portion of the memory clock cycle. The write operation to the write-selected column occurs without any precharging of bit lines in the write-selected column during read and write operations.

The application relates to a low-complexity signal-to-noise ratio estimation method and system based on a lookup table method, which comprises the following steps: acquiring a square second-moment term and a fourth-moment of a to-be-tested signal; extracting a magnitude index and a normalized mantissa of the square second-moment term and the fourth-moment respectively; calculating a base address according to the magnitude index, calculating an offset address according to the normalized mantissa, and splicing the base address and the offset address into a complete memory retrieval address bus; and retrieving a preset block read-write memory according to the complete memory retrieval address bus to output a target signal-to-noise ratio estimation value. The application has the advantages that a lightweight hardware addressing operation is used to replace a traditional high-overhead division operation, underlying logic resources are greatly saved, precision overflow in fixed-pointing is effectively avoided, and system throughput speed is significantly improved.

The present disclosure relates to a data access latency evaluation system and method, which comprises: a parameter configuration module configured to provide memory access parameters during data access latency testing; at least two data access units coupled to the parameter configuration module and to a memory via an on-chip network, and configured to read and write a two-dimensional data matrix in the memory based on the memory access parameters, wherein at least one of the at least two data access units is a pseudo-computing core; a latency data register group coupled to the at least two data access units, and configured to obtain latency data of the at least two data access units during access to the memory; and a latency evaluation module coupled to the latency data register group, and configured to obtain a latency evaluation result based on the latency data of the at least two data access units and preset latency design conditions. The present disclosure helps to improve the testing efficiency of the memory and the on-chip network, and helps to improve the development efficiency of the SoC.

The invention relates to a data access delay evaluation system and method, and the system comprises a parameter configuration module which is used for providing memory access parameters during a data access delay test; the at least two data access units are coupled to the parameter configuration module, are coupled to the memory through the network-on-chip, and are used for reading and writing the two-dimensional data matrix in the memory based on the memory access parameters, and at least one of the at least two data access units is a pseudo computing core; the delay data register group is coupled to the at least two data access units and is used for acquiring delay data of the at least two data access units when the at least two data access units access the memory; and the delay evaluation module is coupled to the delay data register group and is used for obtaining a delay evaluation result according to the delay data of the at least two data access units and a preset delay design condition. According to the invention, the test efficiency of the memory and the network-on-chip can be improved, and the development efficiency of the SoC can be improved.