3 results about "Read-write memory" patented technology

The application discloses an electric read-write memory device based on 180-degree flip of anti-ferromagnetic Neel vector, a preparation method and a read-write method. The electric read-write memory device comprises a substrate layer, an anti-ferromagnetic layer and a spin source layer which are sequentially stacked from bottom to top and constitute a heterostructure. The material of the substrate layer is a single crystal wafer capable of epitaxially growing the anti-ferromagnetic layer. The material of the anti-ferromagnetic layer is a collinear anti-ferromagnetic material with abnormal Hall effect or a staggered magnet with abnormal Hall effect. The material of the spin source layer has a spin current generation capability. The memory utilizes a current pulse to drive 180-degree flip of the Neel vector. The Neel vector before and after the 180-degree flip has two abnormal Hall resistance states of high and low, and can be used for storing information "0" and "1". The application not only enriches the connotation of the interaction between the spin current and the anti-ferromagnetic Neel vector, but also lays a foundation for constructing a high-density, high read-write speed and low-power nonvolatile magnetic random memory.

A static random access memory is provided with dual pump operations in which read operations to a multiplexed column group of bit cells can occur in a first portion of a memory clock cycle and in which write operations to a write select column of the multiplexed column group of bit cells can occur in a second portion of the memory clock cycle. The write operations to the write select column occur during the read and write operations without any pre-charge of bit lines in the write select column.

The application relates to a low-complexity signal-to-noise ratio estimation method and system based on a lookup table method, which comprises the following steps: acquiring a square second-moment term and a fourth-moment of a to-be-tested signal; extracting a magnitude index and a normalized mantissa of the square second-moment term and the fourth-moment respectively; calculating a base address according to the magnitude index, calculating an offset address according to the normalized mantissa, and splicing the base address and the offset address into a complete memory retrieval address bus; and retrieving a preset block read-write memory according to the complete memory retrieval address bus to output a target signal-to-noise ratio estimation value. The application has the advantages that a lightweight hardware addressing operation is used to replace a traditional high-overhead division operation, underlying logic resources are greatly saved, precision overflow in fixed-pointing is effectively avoided, and system throughput speed is significantly improved.