184 results about "Read-write memory" patented technology

A wireless network adapter for establishing wireless communication links between electronic devices. In one embodiment, the wireless network adapter comprises wireless communication circuitry encased in a shell in the form of a detachable molding element of an electronic device. The wireless network adapter further comprises a bus connector adapted to couple the wireless communication circuitry to an expansion bus when the shell is attached to an outer surface of an electronic device. The wireless network adapter is a fully integrated solution further comprising an RF antenna for communication with a wireless network and a radio modem comprising a radio, a receiver, and modulation circuitry. The RF antenna in the wireless network adapter may take one of several forms. The antenna may be a dedicated unit housed within the shell of the wireless network adapter. Alternatively, the antenna may form a part of the outer shell of the adapter or it may form a part of a company logo located on the shell the adapter. The wireless network adapter is installed in an electronic device such as a portable computer. The electronic device comprises, at a minimum, a system microprocessor, an expansion bus, a read-writeable memory device, an input/output device, and an expansion port connected to the expansion bus that is configured to accept the detachable wireless network adapter. Another embodiment of the present invention comprises an electronic device equipped with an external sleeve configured to accept a wireless network adapter insert.

An exercise system includes a local system having an exercise apparatus and an associated local computer, where the local computer controls and monitors the operation and use, respectively, of the exercise apparatus. The system further includes a remote system having a remote computer, and a transmission medium including a telephone line that couples the local system to the remote system for data communication between the local system and the remote system. The remote system may receive local system data from the local system concerning the use of the exercise apparatus, and the local system may receive remote system data from the remote system concerning the operation of the exercise apparatus. The local computer preferably controls the operation of the exercise apparatus based upon a modifiable script stored in a read/write memory of the local computer, which can be updated by the remote system. A method for controlling an exercise apparatus includes running a modifiable script on a local computer to control the use and to monitor the operation of an exercise apparatus, and communicating with a remote system to provide the remote system with data concerning the use of the exercise apparatus. The script is stored in read/write memory of the local computer and remote system data received from the remote system may include at least a portion of a new script to be stored in the read/write memory of the local computer.

The invention presents a memory controller capable of shortening the creation time of address management table at the time of initialization of memory card, while avoiding decline of access speed due to process of writing back the address management table in normal operation.

The memory controller 114 includes a read-write memory 113 for temporarily storing the address management table 112, a memory control unit 122 for writing, in a nonvolatile memory 115, an address management table temporarily stored in the read-write memory and address range specifying information for specifying the changeover destination address range, when the physical block of data writing destination is changed over from a certain address range to other address range, and an address management table generation unit 107 for reading out the distributed management information used for managing the state of physical block included in the address range specified based on the address range specifying information at the time of initialization, and generating the address management table 112 based on the distributed management information being read out.

A multi-reagent pack has a plurality of reagent compartments and further includes a read-write memory chip that carries data pertaining to a particular test protocol that employs reagents from the reagent compartments. Data may be transferred between the reagent pack and an analytic device, and optionally further to a supplier.

Provided are a ring buffer circuit in which a data full state and a data empty state may be correctly detected without depending on whether read and write operations are synchronous or asynchronous with each other, and a control circuit for the ring buffer circuit. The ring buffer circuit includes: a read and write memory having addresses specified by N bits; a write address counter pointer and a read address counter pointer which are provided for the read and write memory to count (N+1)-bit gray codes; and write and read address converter circuits provided to convert the (N+1)-bit gray codes output from the write and read address counter pointers into N-bit addresses which may be directly designated as write and read addresses of the read and write memory.

A system and/or method for simultaneous read/write access of 1-Transistor (1-T) dynamic random access memory (DRAM), which does not rely on a dual-port DRAM to perform read and write accesses within single clock cycle. A single-port 1-T DRAM works with modified design of read sense amplifier to perform both read and write accesses within single clock cycle, thereby retaining high performance and compact size that characterize the 1-T DRAM while allowing simultaneous read/write access that characterizes dual-port memory. Hence, single-port 1-T DRAM constitutes a pseudo dual-port 1-T DRAM that emulates the dual-port DRAM's ability in performing simultaneous read/write memory access of 1-T DRAM.

The object is to increase the efficiency of processing by conferring the residual image function on hardware and to provide an image processing device wherein processing is implemented at higher speed. In an image processing device equipped with an image memory and a control section that writes generated image data to the image memory, there is provided a blend circuit that reads image memory or image data from image memory and attenuates the read image data and that writes this together with newly generated image data into another image memory, thereby producing a residual image effect.

Embodiments of the present invention provide an antenna apparatus, a system, and an adjusting method. The antenna apparatus is configured to be used in conjunction with an RCU (remote control unit, external remote control unit). The antenna apparatus includes a readable and writable memory and a motor. The readable and writable memory is configured to store configuration data of an antenna and antenna information corresponding to the configuration data, where the configuration data is used to control the RCU to drive the motor to move, so as to adjust an electrical down-tilt angle of the antenna.

A micro card and the passive commutate device suitable for micro card, wherein the micro card is a micro card designed in a theory of micro and is configured with micro controller and substrate of repeating read-write memory and transmit part connect electrically with the substrate. The transmit part of the micro card is designed into a universal interface to support the transfer of sign of interface of various application device. The micro card link with a pre-set passive commutate device, a first standard interface disposed on the passive commutate device. The first standard interface is for memory card interface, and connect electrically with universal interface and couple with memory card of application device. By micro card sense automatically, judge the interface type supported by the passive commutate device to switch to corresponding work model to save outer date to repeating read-write memory of micro card. 5.(1). The representative drawing of the present invention is FIG. 2. (2). The brief description of the representative symbol of the representative drawing of the present invention: 1: micro card 103: transmit part (universal interface) 2. passive commutate device 20: main body 201: first standard interface 202: receive zone 203: second standard interface

Embodiments of the invention provide a read-write protection circuit which mainly comprises a memory and a control circuit. The control circuit is provided for determining electric source received by the memory. The memory is provided with a pin for determining an access state of the memory. When the pin receives a high level voltage, the access state of the memory is set as a read-only state; when the pin receives a low level voltage, the access state of the memory is set as a readable-writable state. With the design of the control circuit provided by the present invention, a user of a manufacturing terminal can read and write data in the memory conveniently, and a user of a whole machine terminal only can read the data in the memory.

The invention discloses a tracking path for controlling opening of a sense amplifier and a static random access memory (SRAM) using the tracking path. The tracking path includes a bit line electric-discharge copy module and a leakage current simulation module, wherein the bit line electric-discharge copy module used for simulation of bit line electric-discharge of memory cells in the static random access memory (SRAM) is connected to a control end of the sense amplifier through a copy bit line, and the leakage current simulation module used for simulation of leakage current of the memory cells in the static random access memory (SRAM) is connected to the control end of the sense amplifier through the copy bit line. In the tracking path disclosed in the invention, the leakage current simulation module used for simulation of the leakage current of the memory cells in the static random access memory (SRAM) is added on the basis of a tracking path in the prior art, the increased bit line electric-discharge time caused by the leakage current of other no-read-write memory cells which are in the SRAM and lie in the same column can be compensated by the leakage current simulation module, so that the time delay of SAE (sense amplifier enable) signal after passing through the tracking path is more approximate to the real electric-discharge time of the memory cell bit line, further the opening of the sense amplifier can be effectively controlled, and the reading speed of the SRAM can be accelerated.

An inspection and maintenance data storage and retrieval system features one or more memory buttons mounted in association with an equipment item. Each memory button incorporates a uniquely identified read/write memory chip, and may comprise a contact memory button, an RFID chip, or other type of read-write memory. Technical information useful for inspection and maintenance of the equipment item, plus historical inspection and maintenance information, is stored in a central database computer remote from the equipment item. A memory button probe, used in conjunction with a portable computer, enables storage on the memory buttons of information relating to inspection and maintenance carried out on the equipment item, as well as related technical information. The portable computer is connected to the central database computer, preferably through a wireless Internet connection, thus enabling downloading of technical information from the central database to the portable computer at the point of inspection or maintenance. Information relating to each inspection and maintenance task may be downloaded to the central database computer via the portable computer. The central database computer may be a network server providing authorized users with access to current maintenance and operational status information for the equipment items supported by the system.

The invention relates to a method for high efficiently debugging by using software breakpoint in a Flash memory. A Flash software breakpoint management controller, a Flash procedure downloader and an instruction resolver are arranged in a debugger; the debugger is connected to a target processing system through an ICE (internet communications engine); the debugger is used for controlling the target processing through the ICE, acquiring and modifying the state of a processor, and reading the data of the Flash memory; and the Flash software breakpoint management controller is used for storing and managing the Flash software breakpoint information, controlling the Flash software breakpoint state transition, controlling the operations of creating, deleting, recovering, shielding, enabling and updating the Flash software breakpoint, and controlling the implement of exchanging instruction sets. By using the method for high efficiently debugging by using software breakpoint in a Flash memory, the debugging time is shortened by reducing the Flash erasing operation; especially, the proceeding running from the Flash software breakpoint is as quick as the operation of arranging the software breakpoint in a RAM (random-access memory); the service life is influenced by the Flash erasing operation, thereby being capable of efficiently increasing the service life of Flash by reducing the Flash erasing operation.

The invention discloses a computer system information storing and reading method based on BIOS read-write internal memory, which is characterized by the following: initializing SMBUS controller operation; checking internal memory SPD whether be accessed; checking accuracy of relative read-write operation; writing the storing data into special zone of the internal memory SPD with the right operation; accessing internal memory SPD with SMBUS controller; reading the data; calculating; checking; comparing uniformity with the check bit data in the internal memory SPD; reading the data from the special zone in internal memory SPD with uniform data. This invention possesses high information safety, simple programming and convenient realization, which can bring very big convenient for further development of the computer.

A portable Read-Write Memory with USB interface is disclosed. The portable Read-Write Memory includes an external housing and a control circuit within the housing. The control circuit includes USB interface, flash memory, CPU, and register, wherein the CPU completes address selection and modular conversion, and the ports thereof are connected to USB, flash memory, and register. In addition, the CPU port is also connected to IR module or emitting frequency identification module having sensing antenna.

A water filter communication system and method of using the system. A method of periodically reading water filter data associated with a water filter and retained by the water filter that has been positioned in an appliance includes the steps of: installing a water filter into an engaged position in a filter head assembly within an interior of a cabinet of an appliance that includes a water inlet and a water outlet and periodically, based upon and after a user's interaction with the appliance or the water filter, supplying power from the appliance to the filter read-write memory device engaged to the filter housing; transmitting water filter data to the appliance from the filter read-write memory device, which retains filter information.

The invention discloses a method for simultaneously reading and writing a memory and a data acquisition device thereof. The method comprises the following steps of: dividing the memory into 2-128 segment memory space sections; setting sampling parameters and starting read/write high bit address; writing acquired data into the memory space section corresponding to the current write high bit address; setting the identifier of the memory space section readable after the acquisition is completed; changing the write high bit address of the current memory section; reading data in the memory space section corresponding to the read high bit address; setting the identifier of the memory space section writable after the reading is completed; and changing the read high bit address of the current memory space section. The device comprises a sensor, a double-end random access memory, a signal processing unit, an A/D converting unit, a control logic, and an USB interface chip. With the segmented buffer storage, the invention can read data while storing data, avoids the read/write conflict on the memory, thereby reducing the time of reading and writing data and improving the speed of data acquiring of the device.

The invention discloses a multiple phase addition-comparison-selection forward trace-back Viterbi decoder including a branch metric unit, a multi-phase add compare select unit, a path and a forward survive path storage unit; the branch measuring unit calculates a branch measuring value according to a received signal. The multiple phase addition-comparison-selection forward trace-back Viterbi decoder provided by the invention used for a WLANMIMO-OFDM system can realize multiple-phase processing of addition-comparison-selection according to states of odd and even by increasing few a few subtracters and selectors by 40%.. Besides, the RE method ideology is introduced into the algorithm, decoding delay is reduced by adopting the forward trace-back method and the times of reading, writing and storing memory blocks and the quantity of the memory blocks are reduced. Compared to the traditional forward trace-back method, the pre-traceback method reduces decoding delay by 25%.

An integrated microprocessor system for safety-critical control systems, comprising at least two microprocessor system modules each comprising at least one processor core, a read/write memory and a memory protection unit, and a read-only memory which is jointly assigned to the processor cores of the microprocessor system modules. Each of the microprocessor system modules executes a main program and a monitoring program which may comprise a plurality of subprograms. If the memory protection unit detects unauthorized operations by one of the programs for accessing a separate address area (A, B) of another program, then the respective memory protection unit assigns a separate address area (A, B) of the read/write memory to the main program and to the monitoring program.