12 results about "Read only storage" patented technology

The application discloses a kind of authorization method and system based on multi-factor binding device and host computer software, it is related to embedded device security and software authorization management technical field, and authorization method includes the following steps: S1: upstream vendor securely solidifies core identity information to the read-only storage area of device by factory programming procedure, S2: upstream vendor generates authorization file for device by binding authorization management procedure according to the authorization data of primary customer, S3: primary customer uses the authorization file obtained from upstream vendor, and performs binding operation on device by device binding procedure;With device to establish communication, S4: end user connects host computer software and device, controls device to run;Authorization system includes factory programming procedure, binding authorization management procedure, device binding procedure, host computer procedure.The beneficial effects of the application include realizing the leap from "two-dimensional binding" to "multi-dimensional binding", and providing more control granularity and flexibility.

The embodiment of the invention provides an unexpected use limited use method and equipment, a product, sighting telescope equipment and a medium. The use limiting method for the unexpected purpose comprises the following steps: acquiring scene image data in a current visual field range of sighting telescope equipment; detecting a target feature contained in the scene image data, and judging whether the current use is the unexpected use or not based on the matching degree of the target feature and a landmark feature representing the unexpected use in a sensitive feature library; and if the sighting telescope equipment is not used for the expected purpose, executing a use limiting strategy on the sighting telescope equipment, and performing read-only storage on an event used for the unexpected purpose.

Memories might include a plurality of access lines extending in a first direction and having a first conductivity type, a plurality of conductive regions extending in the first direction and having a second conductivity type, a dielectric overlying the plurality of conductive regions, a plurality of data lines extending in a second direction and overlying the dielectric, and a plurality of contacts, wherein each contact of the plurality of contacts is formed in the dielectric at an intersection of a respective data line and a respective conductive region to connect its respective data line to its respective conductive region, and wherein a number of contacts is less than a number of data lines of the plurality of data lines times a number of access lines of the plurality of access lines.

A read-only memory (ROM) includes a first ROM cell, a second ROM cell, and a third ROM cell. The first ROM cell is configured to store a first data value of a ROM code, and includes a first meta-oxide-semiconductor (MOS) transistor. The second ROM cell is configured to store a second data value of the ROM code, and includes a second MOS transistor, wherein a source node of the second MOS transistor is electrically connected to a drain node of the first MOS transistor. The third ROM cell is configured to store a third data value of the ROM code, and includes a third MOS transistor, wherein a drain node of the third MOS transistor is electrically connected to a source node of the first MOS transistor.

The present application relates to the field of Hall current sensor small current measurement and signal processing. The Hall sensor micro current high-precision measurement system based on template matching comprises a Hall current sensor, a signal conditioning circuit, and an analog-to-digital converter. The Hall current sensor is used to collect pulse signals. The signal conditioning circuit converts the collected pulse signals into standardized signals suitable for the analog-to-digital converter. The analog-to-digital converter converts the standardized signals, i.e. the conditioned analog signals, into digital signals, realizing ADC sampling. The system also comprises a programmable gate array with embedded read-only memory unit, cross-correlation calculation unit, and peak detection unit. The programmable gate array has an internal sliding window data buffer ADC_Buffer[n] with a length of M. ADC_Buffer[n] continuously stores the latest ADC sampling values.

The invention relates to a read-only memory array structure, a read-only memory, a reading method of the read-only memory and electronic equipment. The read-only memory array structure comprises N * M memory units, wherein N and M are integers greater than or equal to 2; wherein the grid electrode of the NMOS transistor of at least one auxiliary storage unit in the N * M storage units is connected to the gating word line of the target storage unit in the N * M storage units, and the drain electrode of the NMOS transistor of at least one auxiliary storage unit is connected to the target word line of the target storage unit; wherein the auxiliary storage unit is a storage unit for storing data 1, and the target storage unit is a storage unit for storing data 0. According to the read-only memory array structure, design optimization is carried out on the read-only memory array structure, when the target memory unit is read, the NMOS transistor of the at least one auxiliary memory unit is started, the NMOS transistor of the at least one auxiliary memory unit and the NMOS transistor of the target memory unit form a parallel pull-down path, discharging is carried out on the target bit line together, and therefore the pull-down capacity is enhanced.

This application discloses a system boot device, method, and chip, belonging to the field of integrated circuit design technology. The device is applied to an embedded system, which includes a read-only memory area, an erasable and rewritable memory area, and multiple hardware devices. The read-only memory area stores a bootloader. The device includes: a boot module for starting the bootloader after the embedded system is powered on; an execution module for loading control information from the erasable and rewritable memory area through the bootloader, the control information indicating the hardware device mapped to each priority level, a first address, and a second address; and updating the initialization logic of the bootloader according to the control information, and performing initialization operations on multiple hardware devices in an orderly manner according to the priority levels indicated by the updated initialization logic, to read the configuration information of the corresponding hardware device from the second address, and configure the read configuration information into the hardware device pointed to by the corresponding first address. The initialization priority of the hardware devices can be flexibly adjusted.

The application discloses a kind of MCM-GPU last stage cache management method and MCM-GPU, the method includes: in GPU module, part LLC is selected as remote LLC, to cache the data stored in read-only storage space of remote GPU module;In response to the program executed, whether real-time judgment has stream processor initiates memory request;If yes, then judge whether memory request accesses read-only storage space, if not, then memory request is sent to the LLC in the corresponding LLC in current GPU module or the LLC in the corresponding remote GPU module, if yes, then judge whether memory request accesses local storage space;If yes, then memory request is sent to the LLC in the corresponding LLC in current GPU module;If not, then memory request is sent to the LLC in the corresponding remote LLC in current GPU module;Judge whether hit, if not, then memory request is sent to the LLC in the corresponding remote GPU module.The application can reduce the number of local access remote storage space and overhead, reduce on-chip network conflict, improve the performance of MCM-GPU.

This invention discloses a dual-mode EEG interaction system and method supporting zero-calibration and online incremental learning, belonging to the fields of human-computer interaction systems, embedded artificial intelligence, and edge computing. The system includes a wearable acquisition front-end and an embedded computing core. The computing core has a read-only storage area and a read-write storage area, which respectively pre-store frozen general backbone network parameters and variable lightweight adapter parameters. The system uses a manifold-aware signal conditioning module to project the EEG covariance matrix onto the Riemann tangent space to eliminate individual differences; a parameter-separated decoding engine extracts common features using the frozen backbone and performs personalized corrections using the adapter; and a dual-mode state machine dynamically switches between zero-calibration statistical adaptation mode and online incremental learning mode based on trigger signals. This invention achieves plug-and-play and online adaptive evolution of the EEG system, reduces the computing power and storage overhead required for online learning at the edge, and improves user experience and system robustness.

The invention discloses a data processing method and a related device, a bootstrap program is stored in a read-only storage unit of an NAND Flash storage chip, an installation file used for installing an application system is stored in a server, and then in response to a triggering operation of starting up equipment for performing data storage through the NAND Flash storage chip, the installation file is stored in the server based on the bootstrap program. And establishing a communication link between the equipment and the server, obtaining the installation file from the server, and then installing the application system in the equipment based on the installation file. Wherein the data stored in the read-only memory unit is not easy to lose after the equipment is powered off, so that the data integrity of the bootstrap program after long-term storage is effectively guaranteed, the installation file stored in the cloud is acquired through the bootstrap program, the application system can be normally installed, the data loss caused by the long-term inventory of the UFS / EMMC chip is avoided, and the service life of the application system is prolonged. Therefore, the problem that the equipment cannot be normally started up is solved, and the safety and the stability of long-term storage of the data in the NAND Flash storage chip are effectively improved.

A semiconductor memory device is formed on a semiconductor substrate including a first memory region, a second memory region and a logic region. A flash memory array is formed in the first memory region and includes an array of magnetoresistive random-access (MRAM) memory cells, each MRAM memory cell including an access transistor coupled to a magnetic tunnel junction (MTJ) storage element. A read-only (ROM) memory array is formed in the second memory region and includes an array of read-only (ROM) memory cells, each ROM memory cell including an access transistor coupled to a short or open circuit as the ROM storage element. A memory peripheral circuit is formed in the logic region. The memory peripheral circuit includes control circuits for receiving input commands and executing memory operations to the memory cells in the flash memory array and the read-only memory array.

The application discloses a hardware breakpoint implementation device and method, belongs to the microprocessor debugging technical field, solves the technical problem that the traditional hardware breakpoint is limited by the hardware resource and cannot realize large-area address monitoring, and the software breakpoint cannot be used in the read-only storage body such as ROM / FLASH. The application realizes the setting and monitoring of 4*32 accurate hardware breakpoints and 4 range hardware breakpoints under the premise of only increasing a small amount of register hardware resources through the combination configuration mode of a main breakpoint address register+sub-address register, and the range breakpoint register. Meanwhile, the application designs a breakpoint flag and address recording mechanism to realize the accurate identification and feedback of the breakpoint triggering. The application greatly improves the number and monitoring coverage range of the hardware breakpoint, has low hardware resource consumption, is suitable for the debugging requirements of various storage bodies such as ROM, FLASH and RAM, and can be widely applied to the program debugging scenes of microprocessors and single-chip microcomputers.