53results about How to "Avoid reading and writing conflicts" patented technology

The embodiment of the invention provides a file system data access method and a file system, the file system comprises at least one computing node and a plurality of storage nodes, and the method comprises the following steps: the computing node sends a mounting request triggered for a target logical volume to a target storage node; the computing node receives a log segment corresponding to the target logical volume and check point storage position information sent by the target storage node; the computing node reads log metadata of the log segment and the check point according to the log segment and check point storage position information so as to recover the data state of the target logical volume; and the computing node performs data access processing based on the data state of the target logical volume. When the plurality of computing nodes access the target logical volume, the plurality of computing nodes can keep good read-write consistency based on the log information of the target logical volume maintained in each storage node, and read-write can be synchronously carried out, so that read-write conflicts are avoided.

The invention discloses a data read-write method and a storage device, which belongs to the field of memories. The method includes determining capacity specifications of a single-port memory, a main memory look-up table and a standby memory look-up table according to the capacity specifications M*W of a false dual-port / dual-port memory to be achieved and the quantity N+1 of the single-port memory, using M/N number of storage units as units, enabling the storage units corresponding to each unit in the main memory look-up table and the standby memory look-up table to be initialized to different values so as to be used for indicating different single-port memories respectively, reading data from an effective single-port memory indicated by a reading address of the main memory look-up table when reading operation and writing operation exist simultaneously and corresponding values of the reading address and a writing address in the main memory look-up table are same, writing data in a standby single-port memory indicated by the writing address of the standby memory look-up table, and identifying the single-port memory where effective data and idle data of the writing address exist. By means of the scheme, an area of the memories is reduced greatly.

The practical example of the invention discloses a read write control circuit with a dual-port RAM, a device and a method thereof, relating to the technical field of storage, and the invention is invented for evading read write conflict problem of the dual-port RAM. The circuit comprises a comparison circuit, a negation gate and a first coincidence gate, wherein the comparison circuit is used to output read screen signals of a storage unit corresponding with bus signals of a second port address, the negation gate is used to inverse the read screen signals of the storage unit which are corresponding with the bus signals of the second port address, one input end of the first coincidence gate receives the read screen signals of the storage unit which are corresponding with the bus signals of the second port address after being inversed, the other input end of the first coincidence gate receives the read enable signals of a second port, and the output end of the first coincidence gate is connected with the read enable end of the second port. The practical example of the invention can be used in chip circuit designing.

The invention discloses a data frame storage management device, and relates to data frame processing technology. The data frame storage management device comprises three parts, namely an inlet fragmentation device, a fragmentation write and read device and a sub-unit management device of a public storage, wherein the inlet fragmentation device caches a data stream, extracts the data stream in a fragmentation mode into fragmented data and sends the fragmented data to the fragmentation write and read device; the fragmentation write and read device writes the fragmented data into the storage according to sequence signals of a timing control circuit, or reads the fragmented data from the storage; and the sub-unit management device of the public storage controls the read-write operation of the fragmentation write-in and read-out device. The data frame storage management device divides the storage into a plurality of basic storage units which serve as basic units for storage, can be allocated with addresses based on a source port and also can be allocated with addresses in a sharing way, the independent use of the addresses is achieved by applying for a release mechanism, the write and read of the data are completed by adopting a sequence isolation method, and the conflict between the read and write is avoided, so the circuits of the whole system are realized simply.

The invention discloses a data push method, a time schedule controller and a data push system for improving the data read-write efficiency of an application server. The embodiments of the invention provide the data push method, which comprises the following steps of receiving at least two data packets which are respectively sent by an interactive application server, and respectively storing the at least two received data packets into a local buffer queue; taking a first data packet from the local buffer queue, sending the first data packet to the application server and making the application server use the first data packet and a storage server to carry out read-write processing; obtaining whether the application server completes read-write processing of the first data packet at the current moment; and if the application server completes read-write processing of the first data packet at the current moment, taking a second data packet from the local buffer queue, sending the second data packet to the application server and making the application server use the second data packet and the storage server to carry out read-write processing.

The invention discloses a star sensor software online fault monitoring system and a monitoring method thereof. The method comprises the following steps of: writing to-be-transmitted star sensor software key data into an FPGA module by a CPU module by utilizing an address mapping manner; after the FPGA module detects that the electric level state of a handshake signal sent by the CPU module changes, sending the star sensor software key data to ground reception equipment by the FPGA module; and analyzing and displaying star sensor software operation condition by the ground reception equipment in real time, and monitoring software faults online. According to the Star sensor software online fault monitoring system and monitoring method thereof, real-time online monitoring is carried out on star sensor software, the fault problems in the software operation process can be timely positioned, so that the visibility of the star sensor software faults is increased and the troubleshooting efficiency of the star sensor software faults is improved.

The invention relates to a data processing technology, and provides a B+ tree-based read-write conflict resolution method and device and a storage medium. The method comprises the following steps: constructing an index file for a target data set, wherein the index file adopts a B+ tree structure and records the root node address of a B+ tree twice at the head of the file; when a write operation isexecuted on a target data set, adding a data identifier, a storage address or a deletion identifier corresponding to the write operation to a tail node of the B+ tree, then creating replica father nodes of all layers for the tail node, and after recording child node addresses, sequentially modifying a root node address of the file header by the replica father nodes of all layers; executing a reading operation on a target data set; judging whether the root node addresses of the file header are the same or not, if yes, accessing the root node by any one or default root node address, and accessing the corresponding sub-nodes layer by layer to complete the reading operation, and if not, respectively utilizing the root node address to complete the reading operation by the available root node address.

The invention discloses a log reading method based on log analysis synchronization and a data synchronization system, and the log reading method comprises the steps of obtaining the current maximum log serial number and current time of a source end database in a polling interval; establishing association between the current maximum log serial number and the current time, and adding the associationto an LSN information chain table; reading a to-be-synchronized log record from a log file, obtaining a log serial number of the to-be-synchronized log record, and obtaining writing time to which theto-be-synchronized log record belongs based on the LSN information chain table; performing strategy log reading and synchronization according to the difference value between the writing time to whichthe log record to be synchronized belongs and the current system time. According to the invention, the log file access positions of the data synchronization process and the database process are staggered through the time difference, and therefore read-write conflicts can be effectively prevented.

The invention provides an airborne PWM signal conversion device and a method. The precision in sampling and generating PWM signals is improved by using a method of combining coarse counting and fine counting; and data communication is carried out by using a DPRAM with dual mailboxes, and the rapidity, the stability and the reliability of data exchange between a flight control unit and a PWM terminal are improved. The device provided by the invention is realized in an FPGA (field programmable gate array), can be applied to different models of remote controllers and different types of unmanned aerial vehicles, and realizes multi-task expansion.

The invention discloses a method and device for realizing Fourier transform. The method comprises the following steps of: calculating data input to a butterfly calculation unit in multi-level butterfly calculation units and carrying out transposition operation on a calculation result acquired through calculation; storing a calculation result after transposition operation to an RAM (Random Access Memory) for the next butterfly calculation unit of the butterfly calculation unit to calculate the calculation result after transposition operation; storing data calculated by the next butterfly calculation unit in a cycle in the same storage position in the RAM in the calculation result after transposition operation and distributing the data attributing to the same butterfly calculation unit in the calculation result after transposition operation in the preset position of the RAM; reading data needed to be calculated in the current cycle from the preset position of each RAM and calculating the read data by the next butterfly calculation unit in each cycle by using the butterfly calculation unit as a unit.

The invention provides a video interface expansion device based on an FPGA. The device comprises the FPGA, a plurality of video interface receiving conversion chips, a first memory, and a CPU. The output end of each video interface receiving conversion chip is connected to the input end of the FPGA. The first memory is connected to the FPGA. The FPGA is connected to the CPU. The invention furtherprovides a video interface expansion method based on the FPGA. The device and the method have the advantages that a video interface can be expanded at a low cost, and the multi-channel video is simultaneously input.

The invention relates to an SSD based on an HBM cache, and the SSD comprises an SSD based on the HBM and DRAM hybrid cache and an SSD based on the HBM cache; the SSD based on the HBM and DRAM hybrid cache mixedly uses the HBM and the DRAM as the cache, the DRAM stores an FTL (File Transfer Layer) mapping table, and the HBM provides a cache function. According to the SSD based on the HBM cache, the HBM is used for replacing a DRAM, and the HBM has the functions of caching data and storing an FTL mapping table. According to the method, the constant read-write bandwidth is ensured in the process of processing write amplification and garbage collection, the read-write time delay is reduced, and the high-concurrency multi-channel video data access efficiency is ensured to a greater extent.

The invention discloses an FAT sharing system and sharing method for a multi-host FAT file system. The system comprises a storage module end and a plurality of host ends, wherein each host end is in communication connection with the storage module end, and each host end is used for sending a read-write command for FAT resources to the storage module end; the storage module end comprises an FAT management module and a storage module; the FAT management module is used for adding the received read-write commands sent by the host ends into a task queue so as to process the read-write commands in the task queue one by one, obtaining the FAT from the storage module, returning the FAT to the host end corresponding to the currently processed read-write commands, and sending the FAT to the host endcorresponding to the currently processed read-write commands. The actual read-write address of the FAT file is stored in the FAT table. According to the technical scheme, the problem that an FAT filesystem does not support multi-host requests is solved.

The embodiment of the invention discloses an asynchronous RAM (Random Access Memory) read-write method and device, terminal equipment and a readable storage medium. Therefore, the asynchronous RAM can ensure that the read operation of the asynchronous RAM is paused (namely, the position of a read pointer Rdr is kept unchanged) under different read-write frequencies under the conditions that the write address at the current moment minus the read address at the current moment is less than a first threshold value and equal to or greater than 0, and the full-write mark of the asynchronous RAM indicates that the asynchronous RAM is not full, the write operation of the asynchronous RAM is kept normal (namely, the write pointer Wdr moves normally). According to the method and the device, the data is ensured to be normally written into the address with empty data, and the distance between the write pointer Wdr and the read pointer Rdr is increased to avoid read-write conflicts, so that the asynchronous RAM can stably read and write the data, and the stability of the storage process is ensured.

The invention discloses a vehicle-mounted radar time sequence generation system and method based on a VPX bus, and belongs to the technical field of radar data processing. The system comprises a timing system and inertial navigation data input processing module, a servo azimuth input processing module, a VPX bus interface processing module, a time sequence generation module, a time sequence dynamic monitoring module and a time sequence output module, wherein the VPX bus interface processing module is respectively connected with the timing system and inertial navigation data input processing module, the servo azimuth input processing module, the time sequence generation module and the upper computer; the time sequence dynamic monitoring module is respectively connected with the VPX bus interface processing module and the time sequence generation module, and the time sequence output module is connected with the time sequence generation module. The system has the advantages that the timesequence generation method is universal, time sequence signals are stable and reliable, time sequence output interfaces are flexible and diverse, the system can be applied to development of various types of vehicle-mounted radars, and the research and development efficiency and reliability of the whole radar are effectively improved.