53results about How to "Avoid reading and writing conflicts" patented technology

The invention discloses a data read-write method and a storage device, which belongs to the field of memories. The method includes determining capacity specifications of a single-port memory, a main memory look-up table and a standby memory look-up table according to the capacity specifications M*W of a false dual-port / dual-port memory to be achieved and the quantity N+1 of the single-port memory, using M / N number of storage units as units, enabling the storage units corresponding to each unit in the main memory look-up table and the standby memory look-up table to be initialized to different values so as to be used for indicating different single-port memories respectively, reading data from an effective single-port memory indicated by a reading address of the main memory look-up table when reading operation and writing operation exist simultaneously and corresponding values of the reading address and a writing address in the main memory look-up table are same, writing data in a standby single-port memory indicated by the writing address of the standby memory look-up table, and identifying the single-port memory where effective data and idle data of the writing address exist. By means of the scheme, an area of the memories is reduced greatly.

The invention discloses a high-precision information processing system for a star sensor. According to the high-precision information processing system, a FPGA module comprises a photoelectric detector time sequence generator module, an image processing module, a protocol layer data interaction control module, a CPU collaborative working interface module, a data management module and a precision temperature control module, wherein the photoelectric detector time sequence generator module is used for transmitting a detector driving signal, the image processing module is used for receiving and processing star map data output by a detector, the protocol layer data interaction control module is used for carrying out protocol interaction with external equipment, the CPU collaborative working interface module is connected to an external CPU processor, and the data management module is used for managing various data packages. The high-precision information processing system has the advantagesthat the calculation load of a CPU is shared, and the parallel information processing capability is remarkably improved; the time sequence control, image background estimation and star point mass center extraction of the photoelectric detector are completed in real time, so that the requirements of real-time image processing and anti-stray-light high-reliability image processing strategies are met; and the temperature of the detector is acquired in real time, a precision temperature control technology for a semiconductor refrigerator is achieved, the integration degree of a circuit system isimproved, the cost is conveniently lowered, the product miniaturization is facilitated, and the measurement precision of the star sensor is improved.

The invention discloses a DSP communication task scheduling system and method, which relate to the field of missile-borne application platforms, including S1, classifying communication tasks according to communication task functions and sub-modules of the DSP communication task scheduling system, and classifying each type of communication task Set the priority; S2, set the task scheduling system running state machine, and control the permission bit of the communication command of each communication task processing process; S3, when the task scheduling system receives the message, perform secondary Cache, set message classification and message response authority. The DSP communication task scheduling system of the present invention, through the improved design of the internal task system architecture, occupies less hardware resources and lower processing time delay than the existing communication task scheduling system, and can well meet the engineering application environment requirements of the missile-borne embedded platform .

The invention relates to a prediction-based low-latency video superimposition frame buffer scheduler, which belongs to the technical field of character video image processing in display devices. The present invention constructs a frame buffer scheduler on the FPGA. The frame buffer scheduler adopts technologies such as full parallelism and pipeline computing, and can reuse a modular design method, mainly including background video buffer, write frame buffer schedule, storage read and write Units for control, background video detection, readout frame prediction scheduling, foreground video detection, foreground video caching, and video overlay. The readout frame prediction scheduling unit further shortens the overlay delay while avoiding frame buffer read and write conflicts through a certain prediction algorithm according to the state information of the three units of writing frame buffer scheduling, background video detection and foreground video detection. The superimposed frame buffer scheduler of the present invention has the characteristics of preventing tearing of the superimposed picture, predictive algorithm parameters can be adjusted and configured online, superimposed delay less than 18 milliseconds, and the like.

The embodiment of the invention discloses a data updating and reading method, device and equipment and a storage medium. The method comprises the steps that a writing thread determines a first data block currently pointed by a reading pointer and a second data block not pointed by the reading pointer; the writing thread updates the data in the second data block and modifies the current direction of the reading pointer to point to the second data block; and if the thread lock state of the reading thread used for reading the first data block is not locked, the writing thread updates the data inthe first data block. According to the embodiment of the invention, if the thread lock state of the reading thread used for reading the first data block is non-locked, there is not the reading threadto read the first data block, and on the condition, the writing thread just updates the first data block, so that the read-write conflicts existing in double buffering are avoided, and the program running performance is improved.

The invention provides a data synchronization system and a data synchronization method. The system comprises a cache file, a reading pointer file and a writing pointer file, arranged on a hard disk. The cache file is used for storing the data to be cached; A read pointer file for storing a read position of cache data to be synchronized at present; A write pointer file for storing a write positionof cache data to be added at present; When data synchronization is carried out, the system reads the reading pointer file, obtains the reading position of the cache data to be synchronized, and readsthe data to the corresponding cache file according to the reading position to complete data synchronization. When adding new cache data, the system reads the write pointer file, obtains the write position of the cache data to be added, and writes the new cache data to the corresponding cache file according to the write position. The invention can ensure that the read and write of the cached file are not in the same position, thus avoiding the read-write conflict.