Read-write control circuit, method and apparatus for two-port RAM

Abstract

The practical example of the invention discloses a read write control circuit with a dual-port RAM, a device and a method thereof, relating to the technical field of storage, and the invention is invented for evading read write conflict problem of the dual-port RAM. The circuit comprises a comparison circuit, a negation gate and a first coincidence gate, wherein the comparison circuit is used to output read screen signals of a storage unit corresponding with bus signals of a second port address, the negation gate is used to inverse the read screen signals of the storage unit which are corresponding with the bus signals of the second port address, one input end of the first coincidence gate receives the read screen signals of the storage unit which are corresponding with the bus signals of the second port address after being inversed, the other input end of the first coincidence gate receives the read enable signals of a second port, and the output end of the first coincidence gate is connected with the read enable end of the second port. The practical example of the invention can be used in chip circuit designing.

Description

technical field [0001] The invention relates to memory technology, in particular to a read-write control circuit, method and device of a dual-port RAM. Background technique [0002] RAM (Random Access Memory, random access memory) can be divided into single-port RAM (SPRAM) and dual-port RAM (DPRAM) according to the number of ports. Dual-port RAM can be divided into synchronous clock RAM and asynchronous clock RAM according to whether the clocks adopted by the two ports are synchronized. In the asynchronous clock RAM, each port has an independent control terminal (port enable terminal, read enable terminal, write enable terminal), address terminal, and data terminal, and the two ports share a memory. [0003] In digital circuits, device characteristics include: setup time and hold time. The setup time is the time required for the input signal to be stable before the effective edge of the clock signal arrives at the input terminal of the device. The hold time is the time t...

AI Technical Summary

Problems solved by technology

[0009] 1. DSP is required to add a "configuration ready flag" for each address parameter, which increases the burden on DSP;

[0010] 2. If the DSP writes the configuration preparation flag by mistake, the function logic will not be able to read the configured parameters;

[0011] 3. It is necessary to add complex control logic of "configuration ready flag"

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