Read-write control circuit, method and apparatus for two-port RAM

A read-write control and dual-port technology, applied in the field of memory, can solve the problems of adding control logic, function logic cannot read parameters, and increasing the burden of DSP

A read-write control and dual-port technology, applied in the field of memory, can solve the problems of adding control logic, function logic cannot read parameters, and increasing the burden of DSP

CN101226767AActive Publication Date: 2008-07-23HONOR DEVICE CO LTD
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  • Read-write control circuit, method and apparatus for two-port RAM
  • Read-write control circuit, method and apparatus for two-port RAM
  • Read-write control circuit, method and apparatus for two-port RAM

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no. 1 example

[0084] The first embodiment of the read-write control method of the dual-port RAM of the present invention, as shown in Figure 8, includes:

[0085] 801. Decode the first port address bus signal to generate a set of first port storage unit selection signals; the set of first port storage unit selection signals is at a high level at the output end corresponding to the first port address bus signal, low on the remaining outputs;

[0086] 802. Perform an AND operation on the group of first port storage unit selection signals and first port write enable signals respectively;

[0087] 803. Reverse respectively a group of first-port storage unit selection signals after AND operation;

[0088] 804. Before at least 3 clock cycles, output a group of first port memory unit selection signals after AND operation as a group of memory unit read mask signals; after at least 3 clock cycles, output a group of first port after inversion The memory cell selection signal is output as a group of...

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Abstract

The practical example of the invention discloses a read write control circuit with a dual-port RAM, a device and a method thereof, relating to the technical field of storage, and the invention is invented for evading read write conflict problem of the dual-port RAM. The circuit comprises a comparison circuit, a negation gate and a first coincidence gate, wherein the comparison circuit is used to output read screen signals of a storage unit corresponding with bus signals of a second port address, the negation gate is used to inverse the read screen signals of the storage unit which are corresponding with the bus signals of the second port address, one input end of the first coincidence gate receives the read screen signals of the storage unit which are corresponding with the bus signals of the second port address after being inversed, the other input end of the first coincidence gate receives the read enable signals of a second port, and the output end of the first coincidence gate is connected with the read enable end of the second port. The practical example of the invention can be used in chip circuit designing.

Description

technical field [0001] The invention relates to memory technology, in particular to a read-write control circuit, method and device of a dual-port RAM. Background technique [0002] RAM (Random Access Memory, random access memory) can be divided into single-port RAM (SPRAM) and dual-port RAM (DPRAM) according to the number of ports. Dual-port RAM can be divided into synchronous clock RAM and asynchronous clock RAM according to whether the clocks adopted by the two ports are synchronized. In the asynchronous clock RAM, each port has an independent control terminal (port enable terminal, read enable terminal, write enable terminal), address terminal, and data terminal, and the two ports share a memory. [0003] In digital circuits, device characteristics include: setup time and hold time. The setup time is the time required for the input signal to be stable before the effective edge of the clock signal arrives at the input terminal of the device. The hold time is the time t...

Claims

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Application Information

Patent Timeline
23 Jul 2008
Publication
CN101226767A
IPC
G11C7/22; G11C8/12; G11C8/10
Inventors
赵宇翔; 王小璐