Frequency conversion circuit of time division duplex system

Abstract

The invention relates to a frequency conversion circuit for a time division duplex (TDD) system. The frequency conversion circuit has a first transmitting end, a first receiving end, a second receiving end, a first transmitting input end, a first receiving output end and a second receiving output end. The frequency conversion circuit comprises a first mixer, a first single-pole double-throw switch, a second single-pole double-throw switch and a second mixer. The first single-pole double-throw switch and the second single-pole double-throw switch are respectively connected at a first end and a second end of the first mixer. The first transmitting end and the first transmitting input end are respectively connected with the first end of the first single-pole double-throw switch and the first end of the second single-pole double-throw switch. The first receiving end and the first receiving output end are respectively connected with the second end of the first single-pole double-throw switch and the second end of the second single-pole double-throw switch.

Description

technical field [0001] The present invention relates to a time division duplex (TDD) communication system, more specifically, to a frequency conversion circuit of the time division duplex system. Background technique [0002] LTE (Long Term Evolution, long-term evolution) is a long-term evolution of the UMTS (Universal Mobile Telecommunications System, Universal Mobile Communications System) technical standard formulated by 3GPP (The 3rd Generation Partnership Project, Third Generation Partnership Project). At present, the commercialization of LTE public network equipment and terminal products is becoming more and more mature, and its frequency band is mainly concentrated in 700-2700MHz. The next-generation mobile communication industry and hotspot applications are in great demand, and industry applications and hotspot applications have dedicated frequency band requirements (frequency bands may be lower than 700MHz) or public network frequency band requirements higher than 2...

AI Technical Summary

Problems solved by technology

The disadvantage of this solution is that: 2 sets of register configuration are required, and the sending and receiving events have certain timing requirements for the driver; the power consumption is relatively large, and the current is about 180mA (chip 210) + 140mA (chip 220) = 320mA when receiving, and about 320mA when transmitting. 180mA (chip 210), there is a time overlap area in the sending state and forwarding state Tx->Rx, and the power consumption is 500mA; using 2 chips, the PCB occupies a large area; the cost is high

The disadvantages of this solution are: 2 sets of register configuration are required, and the sending and receiving events have certain timing requirements for the drive; >Rx has a time overlap area, and the power consumption is 320mA; using 2 chips, the PCB occupies a large area; the cost is high

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