Multi-core processor simulation method and apparatus

Abstract

The invention provides a multi-core processor simulation method and apparatus. The method comprises: performing simulation at a field programmable gate array (FPGA) to generate a target processor core and a shared functional part; and according to an application run by the target processor core in the FPGA, performing simulation to generate at least one false processor core accessing the shared functional part together with the target processor core, wherein the false processor cores are used for generating access requests of accessing the shared functional part, so that the target processor core, the shared functional part and the false processor cores form a multi-core processor. With the adoption of the technical scheme provided by embodiments of the invention, the complexity of simulating the multi-core processor can be lowered and the simulation speed is increased.

Description

technical field [0001] The invention relates to computer technology, in particular to a method and device for simulating a multi-core processor. Background technique [0002] In computer architecture design, because the pros and cons of a design method and the choice of design parameters are difficult to theoretically derive through the method of building a model, it is usually used to quantitatively analyze and simulate the performance of the target machine by running an actual application program. Evaluate. [0003] Simulation speed can be increased by using Field Programmable Gate Array (Field Programmable Gate Array, FPGA for short). The commonly used method of using FPGA to simulate multi-core processors is the simulation method based on FPGA time-division multiplexing. Specifically, for multiple symmetrical processor cores in multi-core processors, only one processor core can be implemented on FPGA, and pass Let multiple processor cores use this real processor core i...

AI Technical Summary

Problems solved by technology

[0005] The invention provides a method and device for simulating a multi-core processor to solve the problems of slow simulation speed and high implementation complexity when simulating a multi-core processor in the prior art

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