Flash Translation Layer (FTL) address mapping method and device

Abstract

The embodiment of the invention discloses a Flash Translation Layer (FTL) address mapping method and device, relates to the technical field of communication, and can solve the problem that a page mapping method in the prior art is complex in implementation process, and thus a reading-writing process is high in delay. The method provided by the invention comprises the steps of dividing a logic address space into a plurality of logic address fields; building a virtual address space; building a page-level mapping table between each logic address field and a virtual address field corresponding to the logic address field, and a block-level mapping table between a virtual block in each virtual address field and a physical block in a physical address space mapped with the virtual block in the virtual address field; when a mainframe reads or writes data, a target logic page address corresponding to the data read or written by the mainframe is acquired; determining a target virtual page address according to the target logic page address and the page-level mapping table; and determining a target physical page address according to the target virtual page address and the block-level mapping table. The method and device provided by the invention are applicable to FTL address mapping.

Description

technical field [0001] The invention relates to the field of communication technology, in particular to a method and device for FTL address mapping. Background technique [0002] Flash memory Flash-based SSD (Solid State Drive, solid state drive) is composed of host interface, processor, memory, channel controller and a set of flash memory Flash chips. The Flash chip includes multiple wafer dies, and each die includes multiple groups plane, each plane includes 2048 block blocks, and each block consists of 256 pages. The read and write granularity of the Flash chip is one page, and the erase granularity is one block. The read and write characteristics are write-after-erase after erasing, that is, the data on the chip cannot be updated in place. The read-write space presented by the SSD, that is, the space used by upper-level users, is the logical address space. The internal read-write space of the SSD is composed of Flash particles, which is called the physical address space...

AI Technical Summary

Problems solved by technology

[0004] Embodiments of the present invention provide a method and device for FTL address mapping, which can solve the problem that the page mapping method in the prior art has a complicated implementation process and leads to high delay in the read and write process

Images